Patents by Inventor Leonardo Ravazzi
Leonardo Ravazzi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6507067Abstract: A flash EEPROM having an array of memory cells which include a common source line connecting together source electrodes of the memory cells. A resistive feedback element is coupled in series between the common source line and a positive potential when the memory cells must be electrically erased. The Flash EEPROM includes a voltage limiting circuit coupled to the common source line for limiting the potential of the common source line to be prescribed maximum value lower than the positive potential.Type: GrantFiled: July 31, 1996Date of Patent: January 14, 2003Assignee: STMicroelectronics S.r.l.Inventors: Lorenzo Fratin, Leonardo Ravazzi, Carlo Riva
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Patent number: 6369406Abstract: Method for localizing point defects causing column leakage currents in a non-volatile memory device including a plurality of memory cells arranged in rows and columns in a matrix structure, source diffusions, and metal lines which connect said source diffusions to each other. Such a method includes the steps of: modifying the memory device in order to make source diffusions independent of each other and each one electrically connected to a respective row; sequentially biasing the single columns of the matrix; localizing the column to which at least one defective cell belongs, as soon as the leakage current flow occurs in the biased column; by keeping biased the localized column, biasing sequentially the single rows of the matrix to the same potential as that of the localized column; localizing a couple of cells, wherein at least one of them involves the point defects, as soon as the leakage current flow does not occur.Type: GrantFiled: May 13, 1999Date of Patent: April 9, 2002Assignee: STMicroelectronics S.r.l.Inventors: Leonardo Ravazzi, Lorenzo Fratin
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Patent number: 6362053Abstract: Flow process for producing non-volatile memories with differentiated removal of the sacrificial oxide in the NO-DPCC diagram including a series of steps that permit the removal of the oxide in two distinct moments from the matrix area and from the circuitry area. In this manner the active circuitry areas are preserved from the danger of breaking the tunnel oxide, thus avoiding the degradation of the quality of the oxides and increasing, in addition, the level of reliability of the device itself.Type: GrantFiled: August 2, 2000Date of Patent: March 26, 2002Assignee: STMicroelectronics S.r.l.Inventors: Leonardo Ravazzi, Carlo Severgnini, Piero Pansana
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Patent number: 6067250Abstract: Method for localizing point defects causing column leakage currents in a non-volatile memory device, said device including a plurality of memory cells arranged in rows and columns in a matrix structure, the columns being connected to drain regions by first contacts, source diffusions, and metal lines which connect the source diffusions to each other by second contacts. The method includes the steps of modifying the memory device in order to eliminate a part of the first contacts and all the second contacts, and to form third contacts, which connect the metal lines to drain regions in rows wherein the first contacts have been eliminated, making the source diffusions independent of each other and halving the initial number of the memory cells; sequentially biasing the single columns of the matrix; sequentially biasing the single rows of the matrix, keeping biased one column; localizing a memory cell which presents the point defects, when the leakage current flow occurs.Type: GrantFiled: May 13, 1999Date of Patent: May 23, 2000Assignee: STMicroelectronics S.R.L.Inventors: Leonardo Ravazzi, Giuseppe Crisenza
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Patent number: 5920776Abstract: A nonvolatile memory having a cell comprising an N.sup.+ type source region and drain region embedded in a P.sup.- type substrate and surrounded by respective P-pockets. The drain and source P-pockets are formed in two different high-angle boron implantation steps designed to optimize implantation energy and dosage for ensuring scalability of the cell and avoiding impairment of the snap-back voltage. The resulting cell also presents a higher breakdown voltage as compared with known cells.Type: GrantFiled: September 11, 1996Date of Patent: July 6, 1999Assignee: SGS-Thomson Microelectronics, S.r.l.Inventors: Lorenzo Fratin, Leonardo Ravazzi, Carlo Riva
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Patent number: 5793675Abstract: A method employing a test structure identical to the memory array whose gate oxide quality is to be determined, except for the fact that the cells are connected electrically parallel to one another. The test structure is so stressed electrically as to extract electrons from the floating gate of the defective-gate-oxide cells and so modify the characteristic of the cell while leaving the charge of the non-defective cells unchanged. In this way, only the threshold of the defective cells is altered. A sub-threshold voltage is then applied to the test structure, and the drain current through the cells, which is related to the presence of at least one defective cell in the structure, is measured. Measurement and analysis of the current-voltage characteristic provides for determining the number of defective cells. The method is suitable for in-line quality control of the gate oxide of EPROM, EEPROM and flash-EEPROM memories.Type: GrantFiled: April 1, 1997Date of Patent: August 11, 1998Assignee: SGS-Thomson Microelectronics S.r.l.Inventors: Paolo Giuseppe Cappelletti, Leonardo Ravazzi
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Patent number: 5712814Abstract: A nonvolatile memory having a cell comprising an N.sup.+ type source region and drain region embedded in a P.sup.- type substrate and surrounded by respective P-pockets. The drain and source P-pockets are formed in two different high-angle boron implantation steps designed to optimize implantation energy and dosage for ensuring scalability of the cell and avoiding impairment of the snap-back voltage. The resulting cell also presents a higher breakdown voltage as compared with known cells.Type: GrantFiled: July 18, 1995Date of Patent: January 27, 1998Assignee: SGS-Thomson Microelectronics S.r.l.Inventors: Lorenzo Fratin, Leonardo Ravazzi, Carlo Riva
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Patent number: 5712816Abstract: A method employing a test structure identical to the memory array whose gate oxide or interpoly dielectric quality is to be determined, except for the fact that the cells are connected electrically parallel to one another. The test structure is subjected to electrical stress of such a value and polarity as to extract electrons from the floating gate of the defective-gate-oxide or defective-interpoly-dielectric cells and so modify the characteristic of the cell while leaving the charge of the non-defective cells unchanged. In this way, only the threshold of the defective cells is altered. A subthreshold voltage is then applied to the test structure, and the drain current through the cells, which is related to the presence of at least one defective cell in the structure, is measured. Measurement and analysis of the current-voltage characteristic provides for determining the number of defective cells.Type: GrantFiled: July 24, 1996Date of Patent: January 27, 1998Assignee: SGS-Thomson Microelectronics S.r.l.Inventors: Paolo Giuseppe Cappelletti, Leonardo Ravazzi
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Patent number: 5604699Abstract: A method employing a test structure identical to the memory array whose gate oxide or interpoly dielectric quality is to be determined, except for the fact that the cells are connected electrically parallel to one another. The test structure is subjected to electrical stress of such a value and polarity as to extract electrons from the floating gate of the defective-gate-oxide or defective-interpoly-dielectric cells and so modify the characteristic of the cell while leaving the charge of the non-defective cells unchanged. In this way, only the threshold of the defective cells is altered. A subthreshold voltage is then applied to the test structure, and the drain current through the cells, which is related to the presence of at least one defective cell in the structure, is measured. Measurement and analysis of the current-voltage characteristic provides for determining the number of defective cells.Type: GrantFiled: May 31, 1995Date of Patent: February 18, 1997Assignee: SGS-Thomson Microelectronics S.r.l.Inventors: Paolo G. Cappelletti, Leonardo Ravazzi
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Patent number: 5515318Abstract: A method employing a test structure identical to the memory array whose gate oxide quality is to be determined, except for the fact that the cells are connected electrically parallel to one another. The test structure is so stressed electrically as to extract electrons from the floating gate of the defective-gate-oxide cells and so modify the characteristic of the cell while leaving the charge of the non-defective cells unchanged. In this way, only the threshold of the defective cells is altered. A sub-threshold voltage is then applied to the test structure, and the drain current through the cells, which is related to the presence of at least one defective cell in the structure, is measured. Measurement and analysis of the current-voltage characteristic provides for determining the number of defective cells. The method is suitable for in-line quality control of the gate oxide of EPROM, EEPROM and flash-EEPROM memories.Type: GrantFiled: June 2, 1995Date of Patent: May 7, 1996Assignee: SGS-Thomson Microelectronics S.r.l.Inventors: Paolo Cappeletti, Leonardo Ravazzi