Abstract: An improved resistor for use in MOS integrated circuits. An opening is formed in an insulative layer which separates two conductive regions. A plasma enhanced chemical vapor deposition of passivation material such as silicon-rich silcon nitride is deposited in the window, contacting both conductive regions and providing resistance in a vertical direction between these regions.A subsequent annealing process involving controlled temperatures and cycle times provides for determining desired resistive values from an equivalent deposition process. Further, a barrier metal layer may be formed between the vertical resistor and the second conductive region.

Abstract: A process for delineating a vertical resistor on a semiconductor device is disclosed. Resistive and diffusion barrier layers are deposited and then etched, first by dry plasma and then by wet bath. The two step etching allows complete removal of the deposited layers with minimal damage to exposed dielectric, silicide, polysilicon or doped regions on the semiconductor.

Abstract: A process for the reduction of defect formation in conductive layers of semiconductor bodies during patterning, alloying and passivation. A film of low temperature spin-on-glass containing dye is formed on the conductive layer prior to patterning and any high temperature process greater than 200 degrees C. Hermetic passivation is achieved by depositing on the conductive layer a composite film consisting of a lower, tensile layer and an upper, compressive layer with the net force of the passivation film being tensile.

Abstract: A process for the reduction of defect formation in conductive layers of semiconductor bodies during patterning, alloying and passivation. A film of low temperature spin-on-glass containing dye is formed on the conductive layer prior to patterning and any high temperature process greater than 200 degrees C. Hermetic passivation is achieved by depositing on the conductive layer a composite film consisting of a lower, tensile layer and an upper, compressive layer with the net force of the passivation film being tensile.

Abstract: In one embodiment, a relatively thin layer of polysilicon is deposited on an underlying region to which spaced-apart electrical contacts are to be made through a subsequently formed relatively thick insulating layer. The polysilicon is selectively masked by a patterned silicon nitride layer in the regions where contact windows are to be formed. The unmasked polysilicon is then converted to a relatively thick insulating layer in an oxidizing step. Thereafter the silicon nitride portions are removed and the remaining polysilicon is utilized to provide conductive regions in the defined windows. In another embodiment, a relatively thick layer of polysilicon is selectively masked and partially converted to silicon dioxide to define both the insulating layer and the conductive regions. In still another embodiment, a relatively thin layer of polysilicon is patterned and then entirely converted to silicon dioxide to form an insulating layer having windows defined therein.