Abstract: A Sin-Cos sensor arrangement comprises a Sin-Cos sensor operably coupled to signal processing logic via a hardware interface. The hardware interface is arranged to provide the signal processing logic with analog sine and cosine waveforms indicative of fine position data and binary counterparts of the analog sine and cosine waveforms (Phase_A and Phase_B) indicative of rough position data. The signal processing logic is arranged to determine a position and speed of the Sin-Cos sensor by compensating for inaccuracies between analog sine and cosine waveforms and their binary counterparts. In this manner, a fully software-based solution provides a fast, efficient and high accuracy position and speed estimation based on the processing of the analog sine and cosine signals and the digital representation thereof of the Sin-Cos sensor.

Abstract: A timer unit includes a timer for timing the period of time the logic circuit has been in the self-test mode. A comparator is connected to the timer, for comparing the period of time with a maximum for the period of time the logic circuit is allowed to be in the self-test mode and outputting an error signal when the period of time exceeds the maximum. The test timer unit further includes a mode detector for detecting a switching of the logic circuit to the self-test mode. The mode detector is connected to the timer, for starting the timer upon the switching to the self-test mode and stopping the timer upon a switching of the logic circuit out of the self-test mode. The timer unit can be used in a system for testing a logic circuit which includes a test routine module containing a set of instructions which forms a test routine for performing a test on a tested part of the logic circuit.

Abstract: A processor system having a processor core configured to control an external apparatus in accordance with a control algorithm; a signal acquisition managing device configured to receive state signals provided by the apparatus, perform corresponding actions, and generate corresponding synchronized command signals; and a peripheral module structured to receive the synchronized command signals and generate output signals to be processed by the processor core in accordance with the control algorithm.

Abstract: A timer unit includes a timer for timing the period of time the logic circuit has been in the self-test mode. A comparator is connected to the timer, for comparing the period of time with a maximum for the period of time the logic circuit is allowed to be in the self-test mode and outputting an error signal when the period of time exceeds the maximum. The test timer unit further includes a mode detector for detecting a switching of the logic circuit to the self-test mode. The mode detector is connected to the timer, for starting the timer upon the switching to the self-test mode and stopping the timer upon a switching of the logic circuit out of the self-test mode. The timer unit can be used in a system for testing a logic circuit which includes a test routine module containing a set of instructions which forms a test routine for performing a test on a tested part of the logic circuit.

Abstract: A processor system having a processor core configured to control an external apparatus in accordance with a control algorithm; a signal acquisition managing device configured to receive state signals provided by the apparatus, perform corresponding actions, and generate corresponding synchronized command signals; and a peripheral module structured to receive the synchronized command signals and generate output signals to be processed by the processor core in accordance with the control algorithm.

Abstract: A Sin-Cos sensor arrangement comprises a Sin-Cos sensor operably coupled to signal processing logic via a hardware interface. The hardware interface is arranged to provide the signal processing logic with analogue sine and cosine waveforms indicative of fine position data and binary counterparts of the analogue sine and cosine waveforms (Phase_A and Phase_B indicative of rough position data. The signal processing logic is arranged to determine a position and speed of the Sin-Cos sensor by compensating for inaccuracies between analogue sine and cosine waveforms and their binary counterparts. In this manner, a fully software-based solution provides a fast, efficient and high accuracy position and speed estimation based on the processing of the analogue sine and cosine signals and the digital representation thereof of the Sin-Cos sensor.

Abstract: The present invention provides immunoselective targeting agents that bind to transporters that are transiently accessible on the surface of neuronal cells, and that deliver compounds selectively to such cells. The invention provides methods of selectively killing, as well as methods of selectively promoting survival of, a neuronal cell.

Abstract: A controller (40) which estimates the coil resistance (R) of an electric motor (10), receives representations of a voltage (u(t)) across a stator coil (11) and of a current (i(t)) through the coil (11). At first, the controller (40) estimates the magnetic flux (&PSgr;E(t2)) in the coil by integrating the difference between u(t) and the product between the current with a preliminary resistance (R) over a predetermined time interval (t1, t2) in which the coil (11) is energized. Second, the controller (40) calculates a resistance error (&Dgr;R) using a known actual flux value &PSgr;A(t2) at the end (t2) of the time interval, the previously estimated magnetic flux &PSgr;E(t2) and the integral of the current over the time interval. Third, the calculator derives the coil resistance (R) from the preliminary resistance (R) and the resistance error (&Dgr;R).

Abstract: An AC-to-DC-converter (100) for driving a dynamic load (160), such as a motor, has a rectifier bridge (110), a coil (120), and a switch (130) to boost an output capacitor (150) by a coil current I(t). The current (I(t)) has periodical minimum values. The converter (100) is controlled by a monitor (170) and a modulator (180). The monitor (170) monitors the converter output (signal 102) during a predetermined monitoring interval (t.sub.M1, t.sub.M2) which is inside a minimum-to-minimum interval of the current (I(t)) and classifies changes (voltage .DELTA.V.sub.OUT) and/or current .DELTA.I.sub.OUT) into a first case (A) where the change exceeds a predetermined threshold (.DELTA.V.sub.TH) and a second case (B) where the change does not exceed the threshold. In order to shape the current (I(t)), in the first case (A), the modulator (180) immediately alters the current (I(t)), and in the second case (B), the modulator (180) alters the current (I(t)) when the current has its next minimum.

Abstract: In a method for operating a brushless motor with commutated stator excitation and permanent rotor field, the stator is initially energized partly. Depending on the polarity of the back electromagnetic force (EMF) in the non-energized stator coil at a predetermined time point (t(n)+T.sub.OFF) and on the occurrence of a EMF zero-crossing event in a following time frame (T.sub.MONITOR), the next stator commutation (t'(n+1)) is scheduled. Thereby, three cases (i)(ii)(iii) are distinguished and detected events (.tau.(n-1)) in previous commutation cycles (n-1) are taken into account.

Abstract: In a method for operating an electric motor especially a permanent magnet motor, the voltage applied to the windings of the stator of the motor are commuted electronically. The timing of the commutation events is determined by sensing and low pass filtering the differential voltages between the windings and detecting the zero crossings of the filtered differential voltages. At the time the zero crossings take place or within a short time afterwards the commutation events take place.