Abstract: An optimized, superscalar microprocessor architecture for supporting graphics operations in addition to the standard microprocessor integer floating point operations is provided. Independent execution paths are provided for different graphics instructions to allow parallel execution of instructions which commonly occur together. The invention also optimizes the use of register file accesses to avoid, as much as possible, interference between graphics instructions needing to access a register file and other instruction accesses which would occur in combination with graphics instructions, thereby avoiding pipeline stalls and allowing parallel execution.

Abstract: A partial store instruction and associated logic for storing selected bytes of a group of bytes in a register to a designated memory location. A mask in a separate register is used to enable particular bytes to be written, with only enabled bytes being written to the final location. The mask can be previously generated as a result of a comparison or other operation. The creation of the mask and the execution of a partial store instruction can also be used as a prefetch instruction, eliminating the need for a separate opcode for a prefetch.

Abstract: A virtual I/O processor (VIOP) is implemented using a programmed I/O (PIO) unit. The PIO unit is complemented by a VIOP interrupt, a VIOP interrupt handler, and a number of VIOP data structures. Preferably, the PIO unit is further complemented with a set of dedicated I/O global registers, a number of VIOP library read/write routines for various I/O device types, and non-blocking read and write operations. During execution, these elements cooperate with each other to perform multiple sequences of programmed I/Os as if they were being performed by a dedicated I/O processor.

Abstract: A method and circuitry for handling status information in a computer is described. If there are additional pipeline states to restore, then a first operation is executed. All traps are disabled for a next advancement of the pipeline. A first logical value is stored into an update bit position associated with a first stage of the pipeline. A value is stored into a status bit position associated with the first stage of the pipeline. If the value of the update bit is not associated with the last stage of the pipeline, then the pipeline is advanced by one stage. The value of the update bit position is propagated unchanged to a next stage of the pipeline and becomes associated with that stage of the pipeline. The value of the status bit position is propagated unchanged to the next stage of the pipeline and becomes associated with that stage of the pipeline. If the value of the update bit is not associated with the last stage of the pipeline, then the above steps are repeated.

Abstract: A method for locking and unlocking a computer address is described. A separate instruction for locking is read. A first value is assigned to a flag to indicate that locking has been requested. An instruction that uses the address is executed. The address is locked such that the address can be accessed by the processor and not by any other processor. A separate instruction for unlocking is read. A second value is assigned to a flag to indicate that unlocking has been requested. A load instruction or a store instruction is executed. The address is unlocked such that the address can be accessed by the processor and by at least one other processor.

Abstract: A translation look-aside buffer is implemented utilizing a four-way set associative cache memory having four lines of 16 sets each. A virtual address tag and its corresponding physical address tag, as well as a number of status bits which control the type of access permitted for a given virtual address, are stored in the translation look-aside buffer. A portion of the inputted virtual address signal is used to provide a virtual address tag and is compared to the virtual address tag in the buffer memory. When the virtual address tag comparison is achieved, the physical address tags are provided as an output from the translation look-aside buffer. Also at the same time, a fault detection circuit performs various fault detection logic on the status bits, depending on the execution cycle being performed, such as read/write cycle or user/supervisor mode.

Abstract: A method for parallel instruction execution in a computer is described. If the computer is executing in the single-instruction mode and the computer encounters a first type of instruction with a dual-instruction mode bit having a first value, then one more single instruction is executed before dual-instruction mode instruction execution begins. The first type of instruction is an instruction having a dual-instruction mode bit. The dual-instruction mode instruction execution occurs in parallel. If the computer is executing in the dual-instruction mode and the computer encounters the first type of instruction with the dual-instruction mode bit having a second value, wherein the second value is different from the first value, then one more dual instruction is executed before single-instruction mode instruction execution resumes.

Abstract: In a microprocessor having a floating-point execution unit, a floating-point bus control apparatus for performing dual-operation instructions includes a multiplier unit having first and second multiplexed operand inputs, an adder unit also having first and second multiplexed operand inputs, a register for storing real and imaginary components of a constant, another register for storing an intermediate result of the multiplier unit and appropriate interconnections. The floating-point unit of the processor supplies first and second instruction source operands and a destination floating-point register. Multiplexers are used to select which operands are to be input to the appropriate operand inputs so as to implement the corresponding dual-operation algorithm.

Abstract: Special purpose graphics instructions are provided to implement linear interpolation of pixel attributes such as a distance (Z) value or color intensity. Multiple fixed-point real number additions are performed in parallel in a 64-bit adder. The real number sums are truncated upon being loaded in a MERGE register, the contents of which are then shifted. By performing two or more of such instructions consecutively, multiple interpolated values are accumulated in the MERGE register.

Abstract: A microprocessor having a pipelined architecture, an onchip data cache, a floating-point unit, a floating-point data latch and an instruction for accessing infrequently used data from an external memory system is disclosed. The instruction comprises a first-in-first-out memory for accumulating data in a pipeline manner, a first circuit means for coupling data from the external bus to the first-in-first-out memory and a second circuit means for transferring the data stored in the first-in-first-out memory to the floating-point data latch. The second circuit means also couples data from the cache to the first-in-first-out memory in the event of a cache hit. Finally, a bus control means is provided for controlling the orderly flow of data in accordance with the architecture of the microprocessor.

Abstract: A method and apparatus for providing program loop control in a data processor employs a special purpose instruction that substantially reduces the program overhead associated with conditional branching at the end of a program loop. The instruction first compares a loop counter with a decrement value. If the loop counter has counted down, a loop condition code, which is stored in a dedicated register bit, is cleared. Otherwise, the loop condition code remains set to indicate that further iterations of the loop are required. The decremented value of the loop counter is then stored in a loop counter register. In parallel with decrementing of the loop counter, a conditional branch is executed based on the value of the loop condition code set in the immediately previous iteration of the loop. If the loop condition code is cleared, i.e. if the loop has been completed, program control proceeds to the instruction following the loop after execution of the next instruction in sequence.

Abstract: Special purpose graphics instructions are provided to facilitate hidden surface elimination. A Z-buffer check instruction performs multiple, simultaneous unsigned-integer (ordinal) comparisons of newly computed distance (Z) values with the contents of a Z-buffer. Distances of points to be drawn are compared with corresponding values in the Z-buffer, and appropriate bits of a pixel mask are then set to designate those pixels for which the points to be drawn are closer (smaller) than the Z-buffer values. Previously calculated bits of the pixel mask are shifted so that consecutive Z-buffer check instructions accumulate their results in the pixel mask register. A pixel store instruction utilizes the pixel mask to update only those pixel locations in a frame buffer which correspond to a point on a newly rendered surface closer than the surface represented by the current pixel value.

Abstract: A digital computer system for selecting and linking multiple separately stored data processing procedures consisting of assembly level commands and for selecting a variable data area from a plurality of variable data areas. The system includes memories for storing the data processing procedures, the variable data areas and linking addresses; a program counter for accessing the memory containing the stored data processing procedures; registers for accessing the memories containing the data and the linking addresses; and a hardware unit which is adapted to execute the assembly level commands contained in selected data processing procedures and to provide addresses to the respective memories and the program counter for accessing the memories and the program counter to select linking addresses, variable data areas and data processing procedures in accordance with assembly level commands in the data processing procedure being executed and previously selected addresses.