Abstract: In alternative embodiment, provided are methods and compositions for treating, ameliorating or preventing diseases and conditions, such as cancer, including cancers associated with stem cells such as, without limitation, myelodysplastic syndrome (MDS) and a myeloproliferative neoplasm like chronic myeloid leukemia (CML) or acute myeloid leukemia (AML), and ablating or killing cancer stem cells. In alternative embodiment, provided are a new set of biomarkers to detect leukemia stem cell reprogramming and CML progression. In alternative embodiment, provided are therapeutic targets for treating myelodysplastic syndrome (MDS) and chronic myeloid leukemia (CML) by targeting edited let-7 transcripts.

Abstract: A two-step SET pulse may be applied to a phase change material of a phase change memory cell in which a first lower SET pulse is applied to make the phase change material dwell at 600K to incubate nuclei near the maximum nucleation rate and then a second higher SET pulse is immediately applied to make the phase change material dwell at 720K to maximize crystal growth. Moreover, the slope of the falling edge of a RESET pulse applied prior to the two-step SET pulse may be adjusted to increase the number of nuclei (e.g., formed with a steeper falling edge) to increase SET efficiency at the expense of a more stable amorphous phase (e.g., formed with a less steep falling edge) that improves data retention.

Abstract: A phase change memory device includes a phase change material portion located between a first electrode and a second electrode, and a crystallization template material portion located between the first electrode and the second electrode in contact with the phase change material portion. The crystallization template material portion and the phase change material portion belong to a same crystal system and have matching lattice spacing, or the crystallization template material portion and the phase change material portion do not belong to the same crystal system, but have a matching translational symmetry along at least one paired lattice plane with a matching lattice spacing.

Abstract: A phase change memory device includes a phase change material portion located between a first electrode and a second electrode, and a crystallization template material portion located between the first electrode and the second electrode in contact with the phase change material portion. The crystallization template material portion and the phase change material portion belong to a same crystal system and have matching lattice spacing, or the crystallization template material portion and the phase change material portion do not belong to the same crystal system, but have a matching translational symmetry along at least one paired lattice plane with a matching lattice spacing.

Abstract: Systems and methods for improving the crystallization of a phase change material of a phase change memory cell are described. A two-step SET pulse may be applied to the phase change material in which a first lower SET pulse is applied to make the phase change material dwell at 600K to incubate nuclei near the maximum nucleation rate and then a second higher SET pulse is immediately applied to make the phase change material dwell at 720K to maximize crystal growth. Moreover, the slope of the falling edge of a RESET pulse applied prior to the two-step SET pulse may be adjusted to increase the number of nuclei (e.g., formed with a steeper falling edge) to increase SET efficiency at the expense of a more stable amorphous phase (e.g., formed with a less steep falling edge) that improves data retention.

Abstract: Systems and methods for improving the crystallization of a phase change material of a phase change memory cell are described. A two-step SET pulse may be applied to the phase change material in which a first lower SET pulse is applied to make the phase change material dwell at 600K to incubate nuclei near the maximum nucleation rate and then a second higher SET pulse is immediately applied to make the phase change material dwell at 720K to maximize crystal growth. Moreover, the slope of the falling edge of a RESET pulse applied prior to the two-step SET pulse may be adjusted to increase the number of nuclei (e.g., formed with a steeper falling edge) to increase SET efficiency at the expense of a more stable amorphous phase (e.g., formed with a less steep falling edge) that improves data retention.

Abstract: Systems and methods for improving the crystallization of a phase change material of a phase change memory cell are described. A two-step SET pulse may be applied to the phase change material in which a first lower SET pulse is applied to make the phase change material dwell at 600K to incubate nuclei near the maximum nucleation rate and then a second higher SET pulse is immediately applied to make the phase change material dwell at 720K to maximize crystal growth. Moreover, the slope of the falling edge of a RESET pulse applied prior to the two-step SET pulse may be adjusted to increase the number of nuclei (e.g., formed with a steeper falling edge) to increase SET efficiency at the expense of a more stable amorphous phase (e.g., formed with a less steep falling edge) that improves data retention.

Abstract: In alternative embodiment, provided are methods and compositions for treating, ameliorating or preventing diseases and conditions, such as cancer, including cancers associated with stem cells such as, without limitation, myelodysplastic syndrome (MDS) and a myeloproliferative neoplasm like chronic myeloid leukemia (CML) or acute myeloid leukemia (AML), and ablating or killing cancer stem cells. In alternative embodiment, provided are a new set of biomarkers to detect leukemia stem cell reprogramming and CML progression. In alternative embodiment, provided are therapeutic targets for treating myelodysplastic syndrome (MDS) and chronic myeloid leukemia (CML) by targeting edited let-7 transcripts.

Abstract: An MRAM memory cell is proposed that is based on spin accumulation torque. One embodiment includes a magnetic tunnel junction, a spin accumulation layer connected to the magnetic tunnel junction and a polarization layer connected to the spin accumulation layer. The polarization layer and the spin accumulation layer use spin accumulation to provide a spin accumulation torque on the free magnetic layer of the magnetic tunnel junction to change direction of magnetization of the free magnetic layer.

Abstract: A magnetic memory cell and a method for implementing the magnetic memory cell for use in Solid-State Drives (SSDs) are provided. A magnetic memory cell includes a first conductor M1, and a second conductor M2 and a programmable area using unpatterned programmable magnetic media. At least one of the conductors M1, M2 is formed of a magnetic material, and the conductor M2 is more conductive than conductor M1. Steering of current is provided for programming the magnetic memory cell.

Abstract: An MRAM memory cell is proposed that is based on spin accumulation torque. One embodiment includes a magnetic tunnel junction, a spin accumulation layer connected to the magnetic tunnel junction and a polarization layer connected to the spin accumulation layer. The polarization layer and the spin accumulation layer use spin accumulation to provide a spin accumulation torque on the free magnetic layer of the magnetic tunnel junction to change direction of magnetization of the free magnetic layer.

Abstract: A magnetic memory integrated with complementary metal oxide semiconductor (CMOS) driving circuits and a method for implementing magnetic memory integrated with complementary metal oxide semiconductor (CMOS) driving circuits for use in Solid-State Drives (SSDs) are provided. A complementary metal oxide semiconductor (CMOS) wafer is provided, and a magnetic memory is formed on top of the CMOS wafer providing a functioning magnetic memory chip.

Abstract: A magnetic memory pillar cell and a method for implementing the magnetic memory cell for use in Solid-State Drives (SSDs) are provided. A magnetic memory cell includes a first conductor M1, and a second conductor M2, the second conductor M1 surrounded by the first conductor M1 and a programmable area using unpatterned programmable magnetic media. At least one of the conductors M1, M2 is formed of a magnetic material, and the conductor M2 is more conductive than conductor M1. An oxide barrier extends between the first conductor M1 and a programmable input to the magnetic memory pillar cell; and the oxide barrier is unpatterned.

Abstract: A method of running a bore-lining tubing string into a bore includes running a tubing string, typically a liner string, into a bore while agitating the string. The agitation may also take place while the tubing is being cemented in the bore. Pressure pulses may be applied to fluid in the bore, which fluid may be cement slurry.

Abstract: A magnetic memory pillar cell and a method for implementing the magnetic memory cell for use in Solid-State Drives (SSDs) are provided. A magnetic memory cell includes a first conductor M1, and a second conductor M2, the second conductor M1 surrounded by the first conductor M1 and a programmable area using unpatterned programmable magnetic media. At least one of the conductors M1, M2 is formed of a magnetic material, and the conductor M2 is more conductive than conductor M1. An oxide barrier extends between the first conductor M1 and a programmable input to the magnetic memory pillar cell; and the oxide barrier is unpatterned.

Abstract: A magnetic memory integrated with complementary metal oxide semiconductor (CMOS) driving circuits and a method for implementing magnetic memory integrated with complementary metal oxide semiconductor (CMOS) driving circuits for use in Solid-State Drives (SSDs) are provided. A complementary metal oxide semiconductor (CMOS) wafer is provided, and a magnetic memory is formed on top of the CMOS wafer providing a functioning magnetic memory chip.

Abstract: A magnetic memory cell and a method for implementing the magnetic memory cell for use in Solid-State Drives (SSDs) are provided. A magnetic memory cell includes a first conductor M1, and a second conductor M2 and a programmable area using unpatterned programmable magnetic media. At least one of the conductors M1, M2 is formed of a magnetic material, and the conductor M2 is more conductive than conductor M1. Steering of current is provided for programming the magnetic memory cell.

Abstract: A magnetic memory pillar cell and a method for implementing the magnetic memory cell for use in Solid-State Drives (SSDs) are provided. A magnetic memory cell includes a first conductor M1, and a second conductor M2, the second conductor M1 surrounded by the first conductor M1 and a programmable area using unpatterned programmable magnetic media. At least one of the conductors M1, M2 is formed of a magnetic material, and the conductor M2 is more conductive than conductor M1. An oxide barrier extends between the first conductor M1 and a programmable input to the magnetic memory pillar cell; and the oxide barrier is unpatterned.

Abstract: A three-dimensional (3D) scalable magnetic memory array and a method for implementing the three-dimensional (3D) scalable magnetic memory array for use in Solid-State Drives (SSDs) are provided. A three-dimensional (3D) scalable magnetic memory array includes an interlayer dielectric (IDL) stack of word planes separated by a respective IDL. A plurality of pillar holes is formed in the IDL stack in a single etch step; each of the pillar holes including an oxide barrier coating, and a first conductor M1, and a second conductor M2 forming magnetic pillar memory cells. The first conductor M1 is formed of a magnetic material, and the second conductor M2 is more electrically conductive than the conductor M1; and each of the magnetic pillar memory cell inside the pillar holes have a programmable area using unpatterned programmable magnetic media proximate to a respective one of the word planes.

Abstract: A method for making a current-perpendicular-to-the-plane magnetoresistive sensor structure produces a top electrode that is “self-aligned” on the top of the sensor and with a width less than the sensor trackwidth. A pair of walls of ion-milling resistant material are fabricated to a predetermined height above the biasing layers at the sensor side edges. A layer of electrode material is then deposited onto the top of the sensor between the two walls. The walls serve as a mask during angled ion milling to remove outer portions of the electrode layer. The height of the walls and the angle of ion milling determines the width of the resulting top electrode. This leaves the reduced-width top electrode located on the sensor. Because of the directional ion milling using walls that are aligned with the sensor side edges, the reduced-width top electrode is self-aligned in the center of the sensor.