Patents by Inventor Lester Chang
Lester Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240160828Abstract: A method of generating an IC layout diagram includes receiving an IC layout diagram including a gate region and a gate via, the gate via being positioned at a location within an active region and along a width of the gate region extending across the active region, receiving a first gate resistance value of the gate region, retrieving a second gate resistance value from a resistance value reference based on the location and the width, using the first and second resistance values to determine that the IC layout diagram does not comply with a design specification, and based on the non-compliance with the design specification, modifying the IC layout diagram.Type: ApplicationFiled: January 24, 2024Publication date: May 16, 2024Inventors: Ke-Ying SU, Jon-Hsu HO, Ke-Wei SU, Liang-Yi CHEN, Wen-Hsing HSIEH, Wen-Koi LAI, Keng-Hua KUO, KuoPei LU, Lester CHANG, Ze-Ming WU
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Publication number: 20240111935Abstract: A method of generating an IC layout diagram includes receiving the IC layout diagram including an active region, a gate region extending across the active region from a first active region edge to a second active region edge, and a gate via positioned at a location along the gate region between the first and second edges, configuring a delta resistance network including the first and second edges, a midpoint between the first and second edges, and resistance values based on the location and first and second edges, and performing a simulation based on the delta resistance network.Type: ApplicationFiled: November 27, 2023Publication date: April 4, 2024Inventors: Ke-Ying SU, Ke-Wei SU, Keng-Hua KUO, Lester CHANG
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Patent number: 11907636Abstract: A method of generating an IC layout diagram includes receiving a first gate resistance value of a gate region in an IC layout diagram, the first gate resistance value corresponding to a location of a gate via positioned within an active region and along a width of the gate region extending across the active region, determining a second gate resistance value based on the location and the width, using the first and second resistance values to determine that the IC layout diagram does not comply with a design specification, and based on the non-compliance with the design specification, modifying the IC layout diagram.Type: GrantFiled: July 8, 2022Date of Patent: February 20, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ke-Ying Su, Jon-Hsu Ho, Ke-Wei Su, Liang-Yi Chen, Wen-Hsing Hsieh, Wen-Koi Lai, Keng-Hua Kuo, Kuopei Lu, Lester Chang, Ze-Ming Wu
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Patent number: 11842135Abstract: A method of generating an integrated circuit (IC) layout diagram of an IC device includes receiving the IC layout diagram of the IC device, the IC layout diagram including a gate region having a width across an active region. The width is divided into a plurality of width segments based on a location of a gate via, and a simulation is performed based on the IC layout diagram and including an effective resistance calculated using at least one width segment of the plurality of width segments.Type: GrantFiled: September 24, 2020Date of Patent: December 12, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ke-Ying Su, Ke-Wei Su, Keng-Hua Kuo, Lester Chang
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Publication number: 20220343054Abstract: A method of generating an IC layout diagram includes receiving a first gate resistance value of a gate region in an IC layout diagram, the first gate resistance value corresponding to a location of a gate via positioned within an active region and along a width of the gate region extending across the active region, determining a second gate resistance value based on the location and the width, using the first and second resistance values to determine that the IC layout diagram does not comply with a design specification, and based on the non-compliance with the design specification, modifying the IC layout diagram.Type: ApplicationFiled: July 8, 2022Publication date: October 27, 2022Inventors: Ke-Ying SU, Jon-Hsu HO, Ke-Wei SU, Liang-Yi CHEN, Wen-Hsing HSIEH, Wen-Koi LAI, Keng-Hua KUO, KuoPei LU, Lester CHANG, Ze-Ming WU
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Patent number: 11392749Abstract: A method of generating a netlist of an IC device includes receiving gate region information of the IC device. The gate region information includes a width of the gate region, the width extending at least from a first edge of an active region to a second edge of the active region, a location of a gate via positioned within the active region and along the width, and a first gate resistance value corresponding to the gate region. The method includes determining a second gate resistance value based on the location and the width, and modifying the netlist based on the second gate resistance value.Type: GrantFiled: November 18, 2020Date of Patent: July 19, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ke-Ying Su, Jon-Hsu Ho, Ke-Wei Su, Liang-Yi Chen, Wen-Hsing Hsieh, Wen-Koi Lai, Keng-Hua Kuo, KuoPei Lu, Lester Chang, Ze-Ming Wu
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Publication number: 20210073454Abstract: A method of generating a netlist of an IC device includes receiving gate region information of the IC device. The gate region information includes a width of the gate region, the width extending at least from a first edge of an active region to a second edge of the active region, a location of a gate via positioned within the active region and along the width, and a first gate resistance value corresponding to the gate region. The method includes determining a second gate resistance value based on the location and the width, and modifying the netlist based on the second gate resistance value.Type: ApplicationFiled: November 18, 2020Publication date: March 11, 2021Inventors: Ke-Ying SU, Jon-Hsu HO, Ke-Wei SU, Liang-Yi CHEN, Wen-Hsing HSIEH, Wen-Koi LAI, Keng-Hua KUO, KuoPei LU, Lester CHANG, Ze-Ming WU
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Publication number: 20210019467Abstract: A method of generating an integrated circuit (IC) layout diagram of an IC device includes receiving the IC layout diagram of the IC device, the IC layout diagram including a gate region having a width across an active region. The width is divided into a plurality of width segments based on a location of a gate via, and a simulation is performed based on the IC layout diagram and including an effective resistance calculated using at least one width segment of the plurality of width segments.Type: ApplicationFiled: September 24, 2020Publication date: January 21, 2021Inventors: Ke-Ying SU, Ke-Wei SU, Keng-Hua KUO, Lester CHANG
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Patent number: 10860769Abstract: An integrated circuit (IC) design method includes receiving a spatial correlation matrix, R, of certain property of post-fabrication IC devices; and deriving a random number generation function g(x, y) such that random numbers for a device at a coordinate (x, y) can be generated by g(x, y) independent of other devices, and all pairs of random numbers satisfy the spatial correlation matrix R. The method further includes receiving an IC design layout having pre-fabrication IC devices, each of the pre-fabrication IC devices having a coordinate and a first value of the property. The method further includes generating random numbers using the coordinates of the pre-fabrication IC devices and the function g(x, y); deriving second values of the property by applying the random numbers to the first values; and providing the second values to an IC simulation tool.Type: GrantFiled: December 19, 2019Date of Patent: December 8, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Katherine Chiang, Cheng Hsiao, Chang-Yu Huang, Juan Yi Chen, Ke-Wei Su, Chung-Kai Lin, Lester Chang, Min-Chie Jeng
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Patent number: 10846456Abstract: A method of generating a netlist of an IC device includes extracting dimensions of a gate region of the IC device, the dimensions including a width of the gate region, the width extending at least from a first edge of an active region to a second edge of the active region, and a distance from a first end of the width to a gate via positioned along the width. A first gate resistance value corresponding to the gate region is received, a second gate resistance value is determined based on the distance and the width, and the netlist is updated based on the first and second gate resistance values.Type: GrantFiled: April 19, 2019Date of Patent: November 24, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Ke-Ying Su, Jon-Hsu Ho, Ke-Wei Su, Liang-Yi Chen, Wen-Hsing Hsieh, Wen-Koi Lai, Keng-Hua Kuo, KuoPei Lu, Lester Chang, Ze-Ming Wu
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Patent number: 10796059Abstract: A method of generating an integrated circuit (IC) layout diagram of an IC device includes receiving a layout diagram of the IC device, the IC layout diagram including a gate region having a width across an active region, and a gate via positioned at a location along the width. The location is used to divide the width into a plurality of width segments, an effective resistance of the gate region is calculated based on the plurality of width segments, and the effective resistance is used to determine whether the IC layout diagram complies with a design specification.Type: GrantFiled: March 6, 2019Date of Patent: October 6, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ke-Ying Su, Ke-Wei Su, Keng-Hua Kuo, Lester Chang
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Publication number: 20200125782Abstract: An integrated circuit (IC) design method includes receiving a spatial correlation matrix, R, of certain property of post-fabrication IC devices; and deriving a random number generation function g(x, y) such that random numbers for a device at a coordinate (x, y) can be generated by g(x, y) independent of other devices, and all pairs of random numbers satisfy the spatial correlation matrix R. The method further includes receiving an IC design layout having pre-fabrication IC devices, each of the pre-fabrication IC devices having a coordinate and a first value of the property. The method further includes generating random numbers using the coordinates of the pre-fabrication IC devices and the function g(x, y); deriving second values of the property by applying the random numbers to the first values; and providing the second values to an IC simulation tool.Type: ApplicationFiled: December 19, 2019Publication date: April 23, 2020Inventors: Katherine Chiang, Cheng Hsiao, Chang-Yu Huang, Juan Yi Chen, Ke-Wei Su, Chung-Kai Lin, Lester Chang, Min-Chie Jeng
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Patent number: 10521538Abstract: An integrated circuit (IC) design method includes receiving a spatial correlation matrix, R, of certain property of post-fabrication IC devices; and deriving a random number generation function g(x, y) such that random numbers for a device at a coordinate (x, y) can be generated by g(x, y) independent of other devices, and all pairs of random numbers satisfy the spatial correlation matrix R. The method further includes receiving an IC design layout having pre-fabrication IC devices, each of the pre-fabrication IC devices having a coordinate and a first value of the property. The method further includes generating random numbers using the coordinates of the pre-fabrication IC devices and the function g(x, y); deriving second values of the property by applying the random numbers to the first values; and providing the second values to an IC simulation tool.Type: GrantFiled: October 26, 2016Date of Patent: December 31, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Katherine Chiang, Cheng Hsiao, Chang-Yu Huang, Juan Yi Chen, Ke-Wei Su, Chung-Kai Lin, Lester Chang, Min-Chie Jeng
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Publication number: 20190340328Abstract: A method of generating a netlist of an IC device includes extracting dimensions of a gate region of the IC device, the dimensions including a width of the gate region, the width extending at least from a first edge of an active region to a second edge of the active region, and a distance from a first end of the width to a gate via positioned along the width. A first gate resistance value corresponding to the gate region is received, a second gate resistance value is determined based on the distance and the width, and the netlist is updated based on the first and second gate resistance values.Type: ApplicationFiled: April 19, 2019Publication date: November 7, 2019Inventors: Ke-Ying SU, Jon-Hsu HO, Ke-Wei SU, Liang-Yi CHEN, Wen-Hsing HSIEH, Wen-Koi LAI, Keng-Hua KUO, KuoPei LU, Lester CHANG, Ze-Ming WU
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Publication number: 20190294750Abstract: A method of generating a layout diagram of an IC device includes receiving a layout diagram of the IC device, the IC layout diagram including a gate region having a width across an active region, and a gate via positioned at a location along the width. The location is used to divide the width into a plurality of width segments, an effective resistance of the gate region is calculated based on the plurality of width segments, and the effective resistance is used to determine whether the IC layout diagram complies with a design specification.Type: ApplicationFiled: March 6, 2019Publication date: September 26, 2019Inventors: Ke-Ying SU, Ke-Wei SU, Keng-Hua KUO, Lester CHANG
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Publication number: 20170316138Abstract: An integrated circuit (IC) design method includes receiving a spatial correlation matrix, R, of certain property of post-fabrication IC devices; and deriving a random number generation function g(x, y) such that random numbers for a device at a coordinate (x, y) can be generated by g(x, y) independent of other devices, and all pairs of random numbers satisfy the spatial correlation matrix R. The method further includes receiving an IC design layout having pre-fabrication IC devices, each of the pre-fabrication IC devices having a coordinate and a first value of the property. The method further includes generating random numbers using the coordinates of the pre-fabrication IC devices and the function g(x, y); deriving second values of the property by applying the random numbers to the first values; and providing the second values to an IC simulation tool.Type: ApplicationFiled: October 26, 2016Publication date: November 2, 2017Inventors: Katherine Chiang, Cheng Hsiao, Chang-Yu Huang, Juan Yi Chen, Ke-Wei Su, Chung-Kai Lin, Lester Chang, Min-Chie Jeng