Abstract: An image sensor architecture provides an SNR in excess of 100 dB, without requiring the use of a mechanical shutter. The circuit components for an active pixel sensor array are separated and arranged vertically in at least two different layers in a hybrid chip structure. The top layer is preferably manufactured using a low-noise PMOS manufacturing process, and includes the photodiode and amplifier circuitry for each pixel. A bottom layer is preferably manufactured using a standard CMOS process, and includes the NMOS pixel circuit components and any digital circuitry required for signal processing. By forming the top layer in a PMOS process optimized for forming low-noise pixels, the pixel performance can be greatly improved, compared to using CMOS. In addition, since the digital circuitry is now separated from the imaging circuitry, it can be formed using a standard CMOS process, which has been optimized for circuit speed and manufacturing cost.

Abstract: An image sensor architecture provides an SNR in excess of 100 dB, without requiring the use of a mechanical shutter. The circuit components for an active pixel sensor array are separated and arranged vertically in at least two different layers in a hybrid chip structure. The top layer is preferably manufactured using a low-noise PMOS manufacturing process, and includes the photodiode and amplifier circuitry for each pixel. A bottom layer is preferably manufactured using a standard CMOS process, and includes the NMOS pixel circuit components and any digital circuitry required for signal processing. By forming the top layer in a PMOS process optimized for forming low-noise pixels, the pixel performance can be greatly improved, compared to using CMOS. In addition, since the digital circuitry is now separated from the imaging circuitry, it can be formed using a standard CMOS process, which has been optimized for circuit speed and manufacturing cost.

Abstract: An image sensor architecture provides an SNR in excess of 100 dB, without requiring the use of a mechanical shutter. The circuit components for an active pixel sensor array are separated and arranged vertically in at least two different layers in a hybrid chip structure. The top layer is preferably manufactured using a low-noise PMOS manufacturing process, and includes the photodiode and amplifier circuitry for each pixel. A bottom layer is preferably manufactured using a standard CMOS process, and includes the NMOS pixel circuit components and any digital circuitry required for signal processing. By forming the top layer in a PMOS process optimized for forming low-noise pixels, the pixel performance can be greatly improved, compared to using CMOS. In addition, since the digital circuitry is now separated from the imaging circuitry, it can be formed using a standard CMOS process, which has been optimized for circuit speed and manufacturing cost.

Abstract: An image sensor architecture provides an SNR in excess of 100 dB, without requiring the use of a mechanical shutter. The circuit components for an active pixel sensor array are separated and arranged vertically in at least two different layers in a hybrid chip structure. The top layer is preferably manufactured using a low-noise PMOS manufacturing process, and includes the photodiode and amplifier circuitry for each pixel. A bottom layer is preferably manufactured using a standard CMOS process, and includes the NMOS pixel circuit components and any digital circuitry required for signal processing. By forming the top layer in a PMOS process optimized for forming low-noise pixels, the pixel performance can be greatly improved, compared to using CMOS. In addition, since the digital circuitry is now separated from the imaging circuitry, it can be formed using a standard CMOS process, which has been optimized for circuit speed and manufacturing cost.

Abstract: An image sensor architecture provides an SNR in excess of 100 dB, without requiring the use of a mechanical shutter. The circuit components for an active pixel sensor array are separated and arranged vertically in at least two different layers in a hybrid chip structure. The top layer is preferably manufactured using a low-noise PMOS manufacturing process, and includes the photodiode and amplifier circuitry for each pixel. A bottom layer is preferably manufactured using a standard CMOS process, and includes the NMOS pixel circuit components and any digital circuitry required for signal processing. By forming the top layer in a PMOS process optimized for forming low-noise pixels, the pixel performance can be greatly improved, compared to using CMOS. In addition, since the digital circuitry is now separated from the imaging circuitry, it can be formed using a standard CMOS process, which has been optimized for circuit speed and manufacturing cost.

Abstract: A color filter array (CFA) and image processing system wherein a color filter overlaying an image sensor has a luminance element (i.e. green filter in RGB space, or yellow in CMY space) that is made larger than the other two chrominance elements (i.e. red, blue or cyan, magenta). Additionally, overlaying micro-lenses may be sized to correspond to the relative sizes of the underlying color filters. The optimized filter array is compatible with existing de-mosaic image processing.

Abstract: A dual sensitivity image sensor provides a standard mode and a high-sensitivity mode of operation via iSoC integration. In addition to boosting sensitivity, the high sensitivity mode also reduces temporal noise thereby optimally boosting the Signal-to-Noise Ratio (SNR) of the image sensor. The circuit does not significantly increase pixel complexity and requires minimal changes to the support circuits in the iSoC including the addition of support and control circuitry to facilitate seamless mode change.

Abstract: A color filter array (CFA) and image processing system wherein a color filter overlaying an image sensor has a luminance element (i.e. green filter in RGB space, or yellow in CMY space) that is made larger than the other two chrominance elements (i.e. red, blue or cyan, magenta). Additionally, overlaying micro-lenses may be sized to correspond to the relative sizes of the underlying color filters. The optimized filter array is compatible with existing de-mosaic image processing.

Abstract: A color filter array (CFA) and image processing system wherein a color filter overlaying an image sensor has a luminance element (i.e. green filter in RGB space, or yellow in CMY space) that is made larger than the other two chrominance elements (i.e. red, blue or cyan, magenta). Additionally, overlaying micro-lenses may be sized to correspond to the relative sizes of the underlying color filters. The optimized filter array is compatible with existing de-mosaic image processing.

Abstract: A method and apparatus for an electronic image sensor having a base exposure, followed by a second or multiple exposures that are formed during signal readout. A timing controller controls the signal readout, such that as each line is read, the second and subsequent exposures are subsequently added to the base exposure to enrich the dynamic range. The image sensor may further include an analog-to-digital converter and noise suppression to further enhance the efficacy of the dynamic range enrichment. The system may also include additional signal processing and scaling functions.

Abstract: A dual sensitivity image sensor provides a standard mode and a high-sensitivity mode of operation via iSoC integration. In addition to boosting sensitivity, the high sensitivity mode also reduces temporal noise thereby optimally boosting the Signal-to-Noise Ratio (SNR) of the image sensor. The circuit does not significantly increase pixel complexity and requires minimal changes to the support circuits in the iSoC including the addition of support and control circuitry to facilitate seamless mode change.

Abstract: A method and apparatus for an electronic image sensor having a base exposure, followed by a second or multiple exposures that are formed during signal readout. A timing controller controls the signal readout, such that as each line is read, the second and subsequent exposures are subsequently added to the base exposure to enrich the dynamic range. The image sensor may further include an analog-to-digital converter and noise suppression to further enhance the efficacy of the dynamic range enrichment. The system may also include additional signal processing and scaling functions.

Abstract: A color filter array (CFA) and image processing system wherein a color filter overlaying an image sensor has a luminance element (i.e. green filter in RGB space, or yellow in CMY space) that is made larger than the other two chrominance elements (i.e. red, blue or cyan, magenta). Additionally, overlaying micro-lenses may be sized to correspond to the relative sizes of the underlying color filters. The optimized filter array is compatible with existing de-mosaic image processing.

Abstract: A sensor may be formed with a transistor comprising a gate that has both n-type and p-type regions to increase the gate work function. In combination with moving the p-type well such that the p-type well only partially dopes the channel of the transistor, the increased gate work function further increases the reset voltage level required to create the reset channel without having to use high doping levels in the critical regions of the sensor structure including the photo-detector and the reset transistor. The source of the reset transistor is partially beneath the n-type region of gate, while the transistor's drain is partially beneath the p-type region of the gate. The channel has a p-type well portion and a substrate portion. This construction of the sensor may eliminate the reset noise associated with the uncertainty of whether the charge left in the transistor's channel will flow back towards the photo-detector after the transistor has been turned off.

Abstract: A CMOS imager system including an active pixel sensor having an access supply which provides distributed feedback, a column buffer (having gain and FPN suppression), and an A/D converter co-located with the sensor such that the effective transmission path between the column buffer (or optional analog PGA) and the A/D converter acts as a resistor, rather than a reactance. The system may further include both an analog gain amplifier stage and a digital programmable amplifier stage.

Abstract: A photodetector is formed in a CMOS circuit using a junction field-effect transistor (JFET). The JFET/CMOS photodetector can be used to create an active pixel sensor for a CMOS digital imager, performing both photodetection and electrical signal amplification, allowing higher fill factors than with conventional APS imagers. A standard CMOS fabrication process is augmented with a small number of steps to integrate the JFET within the pixel, allowing the use of conventional CMOS fabrication plants.

Abstract: A low-noise active pixel circuit is disclosed that efficiently suppresses reset (kTC) noise by using a compact preamplifier consisting of a photodetector and only four MOSFETs of identical polarity, in conjunction with ancillary circuits located on an imager's periphery. The supporting circuits help the simplified pixel circuit to synchronously acquire (i.e., take a snapshot) an image across an imaging array, read the signal with low noise, and efficiently reset the pixel with low noise.

Abstract: A sensor may be formed with a transistor comprising a gate that has both n-type and p-type regions to increase the gate work function. In combination with moving the p-type well such that the p-type well only partially dopes the channel of the transistor, the increased gate work function further increases the reset voltage level required to create the reset channel without having to use high doping levels in the critical regions of the sensor structure including the photo-detector and the reset transistor. The source of the reset transistor is partially beneath the n-type region of gate, while the transistor's drain is partially beneath the p-type region of the gate. The channel has a p-type well portion and a substrate portion. This construction of the sensor may eliminate the reset noise associated with the uncertainty of whether the charge left in the transistor's channel will flow back towards the photo-detector after the transistor has been turned off.

Abstract: An ultra-low noise, high gain interface pixel amplifier is provided with capability for single-photon readout of standard photodetectors at high electrical bandwidths for diverse spectral bandpass from the x-ray to long IR bands. The detector charge modulates a source follower whose output is double sampled to remove correlated noise by a compact stage that also provides optimum level shift for subsequent amplification of the full signal excursion. The level-shifted signal finally drives a compact amplifier that generates a robust end-to-end transimpedance. Single-photon readout of photodetectors at high electrical bandwidths in small pixel areas is thereby facilitated.

Abstract: A low-noise active pixel circuit is disclosed that efficiently suppresses reset (kTC) noise by using a compact preamplifier consisting of a photodetector and only three transistors of identical polarity, in conjunction with ancillary circuits located on an imager's periphery. The use of only three transistors with a tapered reset signal allows the optical area to be increased, while still providing a low-noise imager.