Patents by Inventor Lev Zlotnik

Lev Zlotnik has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multi-reset and multi-clock synchronizer, and synchronous multi-cycle reset synchronization circuit
    Patent number: 11973504
    Abstract: An asynchronous multi-cycle reset synchronization circuit that can correlate any number of resets and synchronous clocks with simultaneous reset de-assertion and removal of reset assertion crossing hazards. The asynchronous multi-cycle reset synchronization circuit can also be paired with a synchronous multi-cycle reset synchronization circuit to correlate same domain asynchronous and synchronous resets. Also described is a synchronous reset multi-cycle synchronization circuit that correlates with any number of asynchronous resets and guarantees simultaneous reset de-assertion.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: April 30, 2024
    Assignee: INTEL CORPORATION
    Inventors: Leon Zlotnik, Lev Zlotnik, Jeremy Anderson
  • Clock crossing FIFO status converged synchronizer
    Patent number: 11741024
    Abstract: A synchronizer that can generate pipeline (e.g., FIFO, LIFO) status in a single step without intermediate synchronization. The status can be an indicator of whether a pipeline is full, empty, almost full, or almost empty. The synchronizer (also referred to as a double-sync or ripple-based pipeline status synchronizer) can be used with any kind of clock crossing pipeline and all kinds of pointer encodings. The double-sync and ripple-based pipeline status synchronizers eliminate costly validation and semi-manual timing closure, suggests better performance and testability, and have lower area and power.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: August 29, 2023
    Assignee: Intel Corporation
    Inventors: Leon Zlotnik, Jeremy Anderson, Lev Zlotnik, Daniel Ballegeer
  • MULTI-RESET AND MULTI-CLOCK SYNCHRONIZER, AND SYNCHRONOUS MULTI-CYCLE RESET SYNCHRONIZATION CIRCUIT
    Publication number: 20220255541
    Abstract: An asynchronous multi-cycle reset synchronization circuit that can correlate any number of resets and synchronous clocks with simultaneous reset de-assertion and removal of reset assertion crossing hazards. The asynchronous multi-cycle reset synchronization circuit can also be paired with a synchronous multi-cycle reset synchronization circuit to correlate same domain asynchronous and synchronous resets. Also described is a synchronous reset multi-cycle synchronization circuit that correlates with any number of asynchronous resets and guarantees simultaneous reset de-assertion.
    Type: Application
    Filed: August 17, 2020
    Publication date: August 11, 2022
    Inventors: Leon ZLOTNIK, Lev ZLOTNIK, Jeremy ANDERSON
  • CLOCK CROSSING FIFO STATUS CONVERGED SYNCHORNIZER
    Publication number: 20210157750
    Abstract: A synchronizer that can generate pipeline (e.g., FIFO, LIFO) status in a single step without intermediate synchronization. The status can be an indicator of whether a pipeline is full, empty, almost full, or almost empty. The synchronizer (also referred to as a double-sync or ripple-based pipeline status synchronizer) can be used with any kind of clock crossing pipeline and all kinds of pointer encodings. The double-sync and ripple-based pipeline status synchronizers eliminate costly validation and semi-manual timing closure, suggests better performance and testability, and have lower area and power.
    Type: Application
    Filed: August 17, 2020
    Publication date: May 27, 2021
    Applicant: Intel Corporation
    Inventors: Leon Zlotnik, Jeremy Anderson, Lev Zlotnik, Daniel Ballegeer