Abstract: A coin cell powered device that includes a unit and one or more interfaces that are configured to interface between the unit, the cell coin and an external capacitor. The unit may include a regulator, a transmitter and a charge pump. The transmitter is configured to transmit signals during a transmission period while receiving power from the regulator, the power originated from the external capacitor. The charge pump is configured to perform, during a charging period, a charging process for charging the external capacitor to a charged voltage that exceeds a voltage of the cell coin, wherein the charging process may include iterations of (a) charging a charge pump capacitor by the coin cell, and (b) discharging the charge pump capacitor thereby charging the external capacitor. The capacitance of the charge pump capacitor is a fraction of a capacitance of the external capacitor. The duration of the charging period exceeds a duration of the transmission period.

Abstract: A coin cell powered device includes a regulator, a transmitter and a charge pump. The transmitter is configured to transmit signals during a transmission period while receiving power from the regulator, the power originated from an external capacitor. The charge pump is configured to perform, during a charging period, a charging process for charging the external capacitor to a charged voltage that exceeds a voltage of a cell coin, wherein the charging process may include iterations of (a) charging a charge pump capacitor by the coin cell, and (b) discharging the charge pump capacitor thereby charging the external capacitor. The capacitance of the charge pump capacitor is a fraction of a capacitance of the external capacitor. The duration of the charging period exceeds a duration of the transmission period.

Abstract: A coin cell powered device that includes a unit and one or more interfaces that are configured to interface between the unit, the cell coin and an external capacitor. The unit may include a regulator, a transmitter and a charge pump. The transmitter is configured to transmit signals during a transmission period while receiving power from the regulator, the power originated from the external capacitor. The charge pump is configured to perform, during a charging period, a charging process for charging the external capacitor to a charged voltage that exceeds a voltage of the cell coin, wherein the charging process may include iterations of (a) charging a charge pump capacitor by the coin cell, and (b) discharging the charge pump capacitor thereby charging the external capacitor. The capacitance of the charge pump capacitor is a fraction of a capacitance of the external capacitor. The duration of the charging period exceeds a duration of the transmission period.

Abstract: Data is transmitted and received in a TDMA frequency hopping system by allocating two or more time slots for transmitting identical data packets, and transmitting the identical data packets in the allocated time slots at different frequencies. This requires the transmission of redundant information but reduces the likelihood of data loss. An adaptive scheme may be employed wherein more time slots are allocated for the repeated data transmissions in areas of poor reception while fewer time slots are allocated for the repeated data transmissions in areas of higher quality reception or when higher bandwidth is required.

Abstract: Data is transmitted and received in a TDMA frequency hopping system by allocating two or more time slots for transmitting identical data packets, and transmitting the identical data packets in the allocated time slots at different frequencies. This requires the transmission of redundant information but reduces the likelihood of data loss. An adaptive scheme may be employed wherein more time slots are allocated for the repeated data transmissions in areas of poor reception while fewer time slots are allocated for the repeated data transmissions in areas of higher quality reception or when higher bandwidth is required.

Abstract: A novel closed loop FET biasing circuit featuring a standard logic control format for operational mode switching between operating states of an FET power amplifier. In a preferred embodiment, an FET gate bias control device is provided for configuring a gate bias circuit in an FET power amplifier to accommodate a broad range of output power levels, wherein the configuration is responsive to a command which establishes an FET bias condition. The gate bias control device of the present invention comprises a circuit having a controllable switching unit which connects a plurality of resistors in the source-drain voltage circuit portion individually or in parallel to provide a multiple of resistance values each corresponding to one of four amplifier operating modes.