Patents by Inventor Lew Chua-Eoan
Lew Chua-Eoan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180073933Abstract: In certain aspects, a method for temperature monitoring comprises receiving temperature readings from a plurality of temperature sensors on a chip, and determining an average or a sum of the temperature readings from the temperature sensors. The sum may be a weighted sum of the temperature readings. The method also comprises computing a temperature at a location on the chip based on the average or sum of the temperature readings. The location may be located at approximately a centroid of the locations of the temperature sensors, an estimated hotspot location on the chip, or another location on the chip.Type: ApplicationFiled: September 12, 2016Publication date: March 15, 2018Inventors: Mustafa Keskin, Masoud Roham, Mehdi Saeidi, Amy Derbyshire, Robert Gilmore, Lew Chua-Eoan
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Patent number: 9768161Abstract: A capacitor includes a semiconductor substrate. The capacitor also includes a first terminal having a fin disposed on a surface of the semiconductor substrate. The capacitor further includes a dielectric layer disposed onto the fin. The capacitor still further includes a second terminal having a FinFET compatible high-K metal gate disposed proximate and adjacent to the fin.Type: GrantFiled: September 17, 2015Date of Patent: September 19, 2017Assignee: QUALCOMM IncorporatedInventors: Rongtian Zhang, Lew Chua-Eoan, Shiqun Gu
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Patent number: 9343127Abstract: A memory device comprises a memory array, at least one row address buffer, a set of row data buffers, a row decoder, an array of sense amplifiers, and a demultiplexer. The memory array comprises data elements organized into rows and columns. Each of the rows is addressable by a row address. Each of the data elements in each of the rows is addressable by a column address. The at least one row address buffer holds a selected row address of a set of successive selected row addresses. The set of row data buffers holds respective contents of selected rows that correspond to the set of successive selected row addresses. The row decoder decodes the selected row address to access a selected row. The array of sense amplifier reads the selected row and transmits content of the selected row to one of the row data buffers through the demultiplexer, and writes the content of the selected row back to the selected row.Type: GrantFiled: January 5, 2016Date of Patent: May 17, 2016Assignee: QUALCOMM IncorporatedInventors: Jian Shen, Liyong Wang, Lew Chua-Eoan
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Publication number: 20160133306Abstract: A memory device comprises a memory array, at least one row address buffer, a set of row data buffers, a row decoder, an array of sense amplifiers, and a demultiplexer. The memory array comprises data elements organized into rows and columns. Each of the rows is addressable by a row address. Each of the data elements in each of the rows is addressable by a column address. The at least one row address buffer holds a selected row address of a set of successive selected row addresses. The set of row data buffers holds respective contents of selected rows that correspond to the set of successive selected row addresses. The row decoder decodes the selected row address to access a selected row. The array of sense amplifier reads the selected row and transmits content of the selected row to one of the row data buffers through the demultiplexer, and writes the content of the selected row back to the selected row.Type: ApplicationFiled: January 5, 2016Publication date: May 12, 2016Inventors: Jian Shen, Liyong Wang, Lew Chua-Eoan
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Patent number: 9281036Abstract: A memory device comprises a memory array, at least one row address buffer, a set of row data buffers, a row decoder, an array of sense amplifiers, and a demultiplexer. The memory array comprises data elements organized into rows and columns. Each of the rows is addressable by a row address. Each of the data elements in each of the rows is addressable by a column address. The at least one row address buffer holds a selected row address of a set of successive selected row addresses. The set of row data buffers holds respective contents of selected rows that correspond to the set of successive selected row addresses. The row decoder decodes the selected row address to access a selected row. The array of sense amplifier reads the selected row and transmits content of the selected row to one of the row data buffers through the demultiplexer, and writes the content of the selected row back to the selected row.Type: GrantFiled: January 8, 2013Date of Patent: March 8, 2016Assignee: QUALCOMM IncorporatedInventors: Jian Shen, Liyong Wang, Lew Chua-Eoan
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Publication number: 20160013180Abstract: A capacitor includes a semiconductor substrate. The capacitor also includes a first terminal having a fin disposed on a surface of the semiconductor substrate. The capacitor further includes a dielectric layer disposed onto the fin. The capacitor still further includes a second terminal having a FinFET compatible high-K metal gate disposed proximate and adjacent to the fin.Type: ApplicationFiled: September 17, 2015Publication date: January 14, 2016Inventors: Rongtian Zhang, Lew Chua-Eoan, Shiqun Gu
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Publication number: 20140195764Abstract: A memory device comprises a memory array, at least one row address buffer, a set of row data buffers, a row decoder, an array of sense amplifiers, and a demultiplexer. The memory array comprises data elements organized into rows and columns. Each of the rows is addressable by a row address. Each of the data elements in each of the rows is addressable by a column address. The at least one row address buffer holds a selected row address of a set of successive selected row addresses. The set of row data buffers holds respective contents of selected rows that correspond to the set of successive selected row addresses. The row decoder decodes the selected row address to access a selected row. The array of sense amplifier reads the selected row and transmits content of the selected row to one of the row data buffers through the demultiplexer, and writes the content of the selected row back to the selected row.Type: ApplicationFiled: January 8, 2013Publication date: July 10, 2014Applicant: QUALCOMM IncorporatedInventors: Jian Shen, Liyong Wang, Lew Chua-Eoan
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Patent number: 8719610Abstract: A computing system includes at least one functional unit and a magnetic random access memory (MRAM) block coupled to the at least one functional unit. The MRAM block is configured to store a functional state of the at least one functional unit during a power down state of the at least one functional unit.Type: GrantFiled: September 23, 2008Date of Patent: May 6, 2014Assignee: QUALCOMM IncorporatedInventors: Matthew Michael Nowak, Lew Chua-Eoan, Seung H Kang
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Publication number: 20130285696Abstract: An on-chip sensor measures dynamic power supply noise, such as voltage droop, on a semiconductor chip. In-situ logic is employed, which is sensitive to noise present on the power supply of functional logic of the chip. Exemplary functional logic includes a microprocessor, adder, and/or other functional logic of the chip. The in-situ logic performs some operation, and the amount of time required for performing that operation (i.e., the operational delay) is sensitive to noise present on the power supply. Thus, by evaluating the operational delay of the in-situ logic, the amount of noise present on the power supply can be measured.Type: ApplicationFiled: June 27, 2013Publication date: October 31, 2013Inventors: Lew Chua-Eoan, Boris Andreev, Yuancheng Christopher Pan, Amirali Shayan, Xiaohua Kong, Mikhail Popovich, Mauricio Calle, IK-Joon Chang
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Patent number: 8497694Abstract: An on-chip sensor measures dynamic power supply noise, such as voltage droop, on a semiconductor chip. In-situ logic is employed, which is sensitive to noise present on the power supply of functional logic of the chip. Exemplary functional logic includes a microprocessor, adder, and/or other functional logic of the chip. The in-situ logic performs some operation, and the amount of time required for performing that operation (i.e., the operational delay) is sensitive to noise present on the power supply. Thus, by evaluating the operational delay of the in-situ logic, the amount of noise present on the power supply can be measured.Type: GrantFiled: February 10, 2010Date of Patent: July 30, 2013Assignee: QUALCOMM IncorporatedInventors: Lew Chua-Eoan, Boris Andreev, Christopher Phan, Amirali Shayan, Xiaohua Kong, Mikhail Popovich, Mauricio Calle, IK-Joon Chang
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Patent number: 8258812Abstract: Systems, circuits and methods for software programmable logic using Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) technology are disclosed. Magnetic tunnel junction (MTJ) storage elements can be formed into input planes and output planes. The input planes and output planes can be coupled together to form complex arrays that allow for the realization of logic functions.Type: GrantFiled: April 4, 2011Date of Patent: September 4, 2012Assignee: QUALCOMM IncorporatedInventors: Lew Chua-Eoan, Matthew Nowak, Seung Kang
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Publication number: 20110254587Abstract: Systems, circuits and methods for software programmable logic using Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) technology are disclosed. Magnetic tunnel junction (MTJ) storage elements can be formed into input planes and output planes. The input planes and output planes can be coupled together to form complex arrays that allow for the realization of logic functions.Type: ApplicationFiled: April 4, 2011Publication date: October 20, 2011Applicant: QUALCOMM INCORPORATEDInventors: Lew Chua-Eoan, Matthew Nowak, Seung H. Kang
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Patent number: 8040154Abstract: Systems, circuits and methods for software programmable logic using Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) technology are disclosed. Magnetic tunnel junction (MTJ) storage elements can be formed into input planes and output planes. The input planes and output planes can be coupled together to form complex arrays that allow for the realization of logic functions.Type: GrantFiled: April 20, 2010Date of Patent: October 18, 2011Inventors: Lew Chua-Eoan, Matthew Nowak, Seung Kang
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Patent number: 7961502Abstract: Electronic circuits use latches including a magnetic tunnel junction (MTJ) structure and logic circuitry arranged to produce a selective state in the MTJ structure. Because the selective state is maintained magnetically, the state of the latch or electronic circuit can be maintained even while power is removed from the electronic device.Type: GrantFiled: December 4, 2008Date of Patent: June 14, 2011Assignee: QUALCOMM IncorporatedInventor: Lew Chua-Eoan
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Publication number: 20100194431Abstract: Systems, circuits and methods for software programmable logic using Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) technology are disclosed. Magnetic tunnel junction (MTJ) storage elements can be formed into input planes and output planes. The input planes and output planes can be coupled together to form complex arrays that allow for the realization of logic functions.Type: ApplicationFiled: April 20, 2010Publication date: August 5, 2010Applicant: QUALCOMM INCORPORATEDInventors: Lew Chua-Eoan, Matthew Nowak, Seung H. Kang
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Patent number: 7728622Abstract: Systems, circuits and methods for software programmable logic using Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) technology are disclosed. Magnetic tunnel junction (MTJ) storage elements can be formed into input planes and output planes. The input planes and output planes can be coupled together to form complex arrays that allow for the realization of logic functions.Type: GrantFiled: March 26, 2008Date of Patent: June 1, 2010Assignee: QUALCOMM IncorporatedInventors: Lew Chua-Eoan, Matthew Nowak, Seung Kang
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Publication number: 20100077244Abstract: A computing system includes at least one functional unit and a magnetic random access memory (MRAM) block coupled to the at least one functional unit. The MRAM block is configured to store a functional state of the at least one functional unit during a power down state of the at least one functional unit.Type: ApplicationFiled: September 23, 2008Publication date: March 25, 2010Applicant: QUALCOMM INCORPORATEDInventors: Matthew Michael Nowak, Lew Chua-Eoan, Seung H. Kang
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Patent number: 7543207Abstract: A full-scan latch is provided that may be used to incorporate design for test functionality in an integrated circuit. The full-scan latch includes a shadow latch, a multiplexer, and a slave latch. The full-scan latch has a test mode and a normal mode. When in the normal mode, the device operates as a transparent latch, passing a data input to its output. When in test mode, the device is operable to pass scan data down a scan chain and to inject scan data into the data path.Type: GrantFiled: June 15, 2007Date of Patent: June 2, 2009Assignee: MIPS Technologies, Inc.Inventors: Lew Chua-Eoan, Era Kasturia Nangia
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Publication number: 20080238475Abstract: Systems, circuits and methods for software programmable logic using Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) technology are disclosed. Magnetic tunnel junction (MTJ) storage elements can be formed into input planes and output planes. The input planes and output planes can be coupled together to form complex arrays that allow for the realization of logic functions.Type: ApplicationFiled: March 26, 2008Publication date: October 2, 2008Applicant: QUALCOMM IncorporatedInventors: Lew Chua-Eoan, Matthew Nowak, Seung H. Kang
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Publication number: 20080022173Abstract: A full-scan latch is provided that may be used to incorporate design for test functionality in an integrated circuit. The full-scan latch includes a shadow latch, a multiplexer, and a slave latch. The full-scan latch has a test mode and a normal mode. When in the normal mode, the device operates as a transparent latch, passing a data input to its output. When in test mode, the device is operable to pass scan data down a scan chain and to inject scan data into the data path.Type: ApplicationFiled: June 15, 2007Publication date: January 24, 2008Applicant: MIPS TECHNOLOGIES, INC.Inventors: Lew Chua-Eoan, Era Nangia