Abstract: A hybrid sample data filter system using quantized data of an analog signal obtained from a delta modulator. A shift register having N preselected taps is fed by the delta modulator. Each of the N taps are fed to a series of AND gates corresponding to the R stages of a coefficient counter and between the stages of the coefficient counter and the AND gates are coefficient setting switches set in accordance with the predetermined weighting of the output taps of the shift register. A ring counter having N stages is also fed to the AND gates for time mutliplexing with each of the stages of the ring counter feeding those AND gates that are fed by the corresponding tap of the shift register. Each of the AND gates fed by the same stage of the R stage coefficient counter is combined in one of a series of N-input OR gates, the output of which is fed to a R-input digital-to-analog converter. A demodulating filter is then connected to the output of the digital-to-analog filter.

Abstract: A sample data filter using a delta modulator to feed a shift register of which selected outputs are pulsewidth weighted. Each of the coefficient multipliers include a flip-flop fed by one of the taps of the shift register and triggered by a clock. A synchronous counter, common to each of the multipliers, is fed to a NAND gate that clears the flip-flop. Interposed between the counter and the NAND gate are a series of switches, one for each stage of the counter. The flip-flop controls a switch to a source of reference voltage and the output of this switch controlled voltage from each of the multipliers is summed and fed to a demodulator.