Abstract: A fault tolerant three port communications module has two control ports for receiving commands from two computers, and a communications port for transferring data over a communications channel in response to the commands. Each control port includes a select line which carries a select signal with true and false states, mode lines which carry codes that represent the commands, and a write line which carries a respective pulse in sync with each of the codes. The select line, mode lines, and write line of each control port are coupled in the module to a respective inter-processor command decoder having a lead stage and a trail stage.

Abstract: A mechanism in a computer system translates a program-generated virtual address into a real address of at least a portion, such as a byte, of a segment of the storage of the computer system. The translation mechanism is operable in either of two modes for forming the real storage address. In either mode of operation of the translation mechanism, a first portion of the virtual address is utilized to select a predetermined one of a plurality of segment descriptors, each having a first field portion and a second field portion.