Patents by Inventor Li-Chieh Wu
Li-Chieh Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210257248Abstract: A method includes forming a first conductive feature over a semiconductor substrate, forming an ILD layer over the first conductive feature, patterning the ILD layer to form a trench, and forming a conductive layer over the patterned ILD layer to fill the trench. The method further includes polishing the conductive layer to form a via contact configured to interconnect the first conductive feature with a second conductive feature, where polishing the conductive layer exposes a top surface of the ILD layer, polishing the exposed top surface of the ILD layer, such that a top portion of the via contact protrudes from the exposed top surface of the ILD layer, and forming the second conductive feature over the via contact, such that the top portion of the via contact extends into the second conductive feature.Type: ApplicationFiled: July 31, 2020Publication date: August 19, 2021Inventors: Pang-Sheng Chang, Chao-Hsun Wang, Kuo-YI Chao, Fu-Kai Yang, Mei-Yun Wang, Li-Chieh Wu, Chun-Wei Hsu
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Publication number: 20210210383Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming a conductive feature over a semiconductor substrate and forming a dielectric layer over the conductive feature. The method also includes forming an opening in the dielectric layer to expose the conductive feature. The method further includes forming a conductive material to overfill the opening. In addition, the method includes thinning the conductive material using a chemical mechanical polishing process. A slurry used in the chemical mechanical polishing process includes an iron-containing oxidizer that oxidizes a portion of the conductive material.Type: ApplicationFiled: March 19, 2021Publication date: July 8, 2021Inventors: Li-Chieh Wu, Kuo-Hsiu Wei, Kei-Wei Chen, Tang-Kuei Chang, Chia Hsuan Lee, Jian-Ci Lin
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Publication number: 20210183688Abstract: Methods of forming a slurry and methods of performing a chemical mechanical polishing (CMP) process utilized in manufacturing semiconductor devices, as described herein, may be performed on semiconductor devices including integrated contact structures with ruthenium (Ru) plug contacts down to a semiconductor substrate. The slurry may be formed by mixing a first abrasive, a second abrasive, and a reactant with a solvent. The first abrasive may include a first particulate including titanium dioxide (TiO2) particles and the second abrasive may include a second particulate that is different from the first particulate. The slurry may be used in a CMP process for removing ruthenium (Ru) materials and dielectric materials from a surface of a workpiece resulting in better WiD loading and planarization of the surface for a flat profile.Type: ApplicationFiled: February 26, 2021Publication date: June 17, 2021Inventors: Chia Hsuan Lee, Chun-Wei Hsu, Chia-Wei Ho, Chi-Hsiang Shen, Li-Chieh Wu, Jian-Ci Lin, Chi-Jen Liu, Yi-Sheng Lin, Yang-Chun Cheng, Liang-Guang Chen, Kuo-Hsiu Wei, Kei-Wei Chen
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Patent number: 10957587Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming a conductive feature over a semiconductor substrate and forming a dielectric layer over the conductive feature. The method also includes forming an opening in the dielectric layer to expose the conductive feature. The method further includes forming a conductive material to overfill the opening. In addition, the method includes thinning the conductive material using a chemical mechanical polishing process. A slurry used in the chemical mechanical polishing process includes an iron-containing oxidizer that oxidizes a portion of the conductive material.Type: GrantFiled: June 24, 2019Date of Patent: March 23, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Chieh Wu, Kuo-Hsiu Wei, Kei-Wei Chen, Tang-Kuei Chang, Chia Hsuan Lee, Jian-Ci Lin
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Publication number: 20210082688Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method further includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method further includes removing the first oxide layer using a H3PO4 solution.Type: ApplicationFiled: November 10, 2020Publication date: March 18, 2021Inventors: Shich-Chang Suen, Li-Chieh Wu, Chi-Jen Liu, He Hui Peng, Liang-Guang Chen, Yung-Chung Chen
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Patent number: 10937691Abstract: Methods of forming a slurry and methods of performing a chemical mechanical polishing (CMP) process utilized in manufacturing semiconductor devices, as described herein, may be performed on semiconductor devices including integrated contact structures with ruthenium (Ru) plug contacts down to a semiconductor substrate. The slurry may be formed by mixing a first abrasive, a second abrasive, and a reactant with a solvent. The first abrasive may include a first particulate including titanium dioxide (TiO2) particles and the second abrasive may include a second particulate that is different from the first particulate. The slurry may be used in a CMP process for removing ruthenium (Ru) materials and dielectric materials from a surface of a workpiece resulting in better WiD loading and planarization of the surface for a flat profile.Type: GrantFiled: September 3, 2019Date of Patent: March 2, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia Hsuan Lee, Chun-Wei Hsu, Chia-Wei Ho, Chi-Hsiang Shen, Li-Chieh Wu, Jian-Ci Lin, Chi-Jen Liu, Yi-Sheng Lin, Yang-Chun Cheng, Liang-Guang Chen, Kuo-Hsiu Wei, Kei-Wei Chen
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Patent number: 10916473Abstract: A method includes forming a first dielectric layer over a wafer, etching the first dielectric layer to form an opening, filling a tungsten-containing material into the opening, and performing a Chemical Mechanical Polish (CMP) on the wafer. After the CMP, a cleaning is performed on the wafer using a weak base solution.Type: GrantFiled: October 17, 2019Date of Patent: February 9, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Hao Chung, Chang-Sheng Lin, Kuo-Feng Huang, Li-Chieh Wu, Chun-Chieh Lin
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Patent number: 10847359Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method further includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method further includes removing the first oxide layer using a H3PO4 solution.Type: GrantFiled: April 20, 2017Date of Patent: November 24, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shich-Chang Suen, Li-Chieh Wu, Chi-Jen Liu, He Hui Peng, Liang-Guang Chen, Yung-Chung Chen
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Patent number: 10755934Abstract: A chemical mechanical polishing (CMP) system and associated semiconductor fabrication methods are disclosed herein. An exemplary method includes performing a planarization process in a polishing unit of a CMP system to planarize a surface of a material layer using a CMP slurry. The method further includes, after performing the planarization process, performing a buffing process in the polishing unit of the CMP system to buff the surface of the material layer using an ozone gas dissolved in deionized water (O3/DIW) solution. The method further includes controlling the performing of the planarization process and the performing of the buffing process, such that the CMP slurry is received by the polishing unit from a first pipeline during the planarization process and the O3/DIW solution is received by the polishing unit from a second pipeline during the buffing process.Type: GrantFiled: December 11, 2019Date of Patent: August 25, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shich-Chang Suen, Chi-Jen Liu, Ying-Liang Chuang, Li-Chieh Wu, Liang-Guang Chen, Ming-Liang Yen
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Patent number: 10643892Abstract: The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.Type: GrantFiled: May 31, 2018Date of Patent: May 5, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Chieh Wu, Tang-Kuei Chang, Kuo-Hsiu Wei, Kei-Wei Chen, Ying-Lang Wang, Su-Hao Liu, Kuo-Ju Chen, Liang-Yin Chen, Huicheng Chang, Ting-Kui Chang, Chia Hsuan Lee
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Publication number: 20200118823Abstract: A chemical mechanical polishing (CMP) system and associated semiconductor fabrication methods are disclosed herein. An exemplary method includes performing a planarization process in a polishing unit of a CMP system to planarize a surface of a material layer using a CMP slurry. The method further includes, after performing the planarization process, performing a buffing process in the polishing unit of the CMP system to buff the surface of the material layer using an ozone gas dissolved in deionized water (O3/DIW) solution. The method further includes controlling the performing of the planarization process and the performing of the buffing process, such that the CMP slurry is received by the polishing unit from a first pipeline during the planarization process and the O3/DIW solution is received by the polishing unit from a second pipeline during the buffing process.Type: ApplicationFiled: December 11, 2019Publication date: April 16, 2020Inventors: Shich-Chang SUEN, Chi-Jen LIU, Ying-Liang CHUANG, Li-Chieh WU, Liang-Guang CHEN, Ming-Liang YEN
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Publication number: 20200105580Abstract: Methods of forming a slurry and methods of performing a chemical mechanical polishing (CMP) process utilized in manufacturing semiconductor devices, as described herein, may be performed on semiconductor devices including integrated contact structures with ruthenium (Ru) plug contacts down to a semiconductor substrate. The slurry may be formed by mixing a first abrasive, a second abrasive, and a reactant with a solvent. The first abrasive may include a first particulate including titanium dioxide (TiO2) particles and the second abrasive may include a second particulate that is different from the first particulate. The slurry may be used in a CMP process for removing ruthenium (Ru) materials and dielectric materials from a surface of a workpiece resulting in better WiD loading and planarization of the surface for a flat profile.Type: ApplicationFiled: September 3, 2019Publication date: April 2, 2020Inventors: Chia Hsuan Lee, Chun-Wei Hsu, Chia-Wei Ho, Chi-Hsiang Shen, Li-Chieh Wu, Jian-Ci Lin, Chi-Jen Liu, Yi-Sheng Lin, Yang-Chun Cheng, Liang-Guang Chen, Kuo-Hsiu Wei, Kei-Wei Chen
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Publication number: 20200051855Abstract: A method includes forming a first dielectric layer over a wafer, etching the first dielectric layer to form an opening, filling a tungsten-containing material into the opening, and performing a Chemical Mechanical Polish (CMP) on the wafer. After the CMP, a cleaning is performed on the wafer using a weak base solution.Type: ApplicationFiled: October 17, 2019Publication date: February 13, 2020Inventors: Chien-Hao Chung, Chang-Sheng Lin, Kuo-Feng Huang, Li-Chieh Wu, Chun-Chieh Lin
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Publication number: 20200043786Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming a conductive feature over a semiconductor substrate and forming a dielectric layer over the conductive feature. The method also includes forming an opening in the dielectric layer to expose the conductive feature. The method further includes forming a conductive material to overfill the opening. In addition, the method includes thinning the conductive material using a chemical mechanical polishing process. A slurry used in the chemical mechanical polishing process includes an iron-containing oxidizer that oxidizes a portion of the conductive material.Type: ApplicationFiled: June 24, 2019Publication date: February 6, 2020Inventors: Li-Chieh Wu, Kuo-Hsiu Wei, Kei-Wei Chen, Tang-Kuei Chang, Chia Hsuan Lee, Jian-Ci Lin
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Patent number: 10515808Abstract: A chemical mechanical polishing (CMP) system includes an O3/DIW generator, a polishing unit, and a cleaning unit. The O3/DIW generator is configured to generate an O3/DIW solution including ozone gas (O3) dissolved in deionized water (DIW). The polishing unit includes components for buffing a surface of a semiconductor structure, and a pipeline coupled to the O3/DIW generator to receive the O3/DIW solution for the buffing. The cleaning unit is coupled to the O3/DIW generator and is configured to clean the surface of the semiconductor structure using the O3/DIW solution.Type: GrantFiled: September 16, 2016Date of Patent: December 24, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shich-Chang Suen, Chi-Jen Liu, Ying-Liang Chuang, Li-Chieh Wu, Liang-Guang Chen, Ming-Liang Yen
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Publication number: 20190385909Abstract: The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.Type: ApplicationFiled: August 30, 2019Publication date: December 19, 2019Inventors: Li-Chieh Wu, Tang-Kuei Chang, Kuo-Hsiu Wei, Kei-Wei Chen, Ying-Lang Wang, Su-Hao Liu, Kuo-Ju Chen, Liang-Yin Chen, Huicheng Chang, Ting-Kui Chang, Chia Hsuan Lee
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Patent number: 10510594Abstract: A method includes forming a first dielectric layer over a wafer, etching the first dielectric layer to form an opening, filling a tungsten-containing material into the opening, and performing a Chemical Mechanical Polish (CMP) on the wafer. After the CMP, a cleaning is performed on the wafer using a weak base solution.Type: GrantFiled: July 31, 2018Date of Patent: December 17, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Hao Chung, Chang-Sheng Lin, Kuo-Feng Huang, Li-Chieh Wu, Chun-Chieh Lin
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Publication number: 20190371664Abstract: The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.Type: ApplicationFiled: May 31, 2018Publication date: December 5, 2019Inventors: Li-Chieh Wu, Tang-Kuei Chang, Kuo-Hsiu Wei, Kei-Wei Chen, Ying-Lang Wang, Su-Hao Liu, Kuo-Ju Chen, Liang-Yin Chen, Huicheng Chang, Ting-Kui Chang, Chia Hsuan Lee
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Publication number: 20180350675Abstract: A method includes forming a first dielectric layer over a wafer, etching the first dielectric layer to form an opening, filling a tungsten-containing material into the opening, and performing a Chemical Mechanical Polish (CMP) on the wafer. After the CMP, a cleaning is performed on the wafer using a weak base solution.Type: ApplicationFiled: July 31, 2018Publication date: December 6, 2018Inventors: Chien-Hao Chung, Chang-Sheng Lin, Kuo-Feng Huang, Li-Chieh Wu, Chun-Chieh Lin
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Patent number: 10109523Abstract: A method includes forming a first dielectric layer over a wafer, etching the first dielectric layer to form an opening, filling a tungsten-containing material into the opening, and performing a Chemical Mechanical Polish (CMP) on the wafer. After the CMP, a cleaning is performed on the wafer using a weak base solution.Type: GrantFiled: December 30, 2016Date of Patent: October 23, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Hao Chung, Chang-Sheng Lin, Kuo-Feng Huang, Li-Chieh Wu, Chun-Chieh Lin