Patents by Inventor Li-Fu Chang
Li-Fu Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10790272Abstract: Aspects of the disclosure are directed to a circuit. In accordance with one aspect, the circuit includes a first layer, wherein the first layer includes two-dimensional (2D) shapes; a second layer coupled adjacent to the first layer through at least one via hole, wherein the second layer includes only one-dimensional (1D) shapes; a shared drain terminal; and a source terminal termination.Type: GrantFiled: July 30, 2018Date of Patent: September 29, 2020Assignee: QUALCOMM IncorporatedInventors: Harmeet Sobti, Mehrdad Manesh, Li-Fu Chang
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Publication number: 20190043850Abstract: Aspects of the disclosure are directed to a circuit. In accordance with one aspect, the circuit includes a first layer, wherein the first layer includes two-dimensional (2D) shapes; a second layer coupled adjacent to the first layer through at least one via hole, wherein the second layer includes only one-dimensional (1D) shapes; a shared drain terminal; and a source terminal termination.Type: ApplicationFiled: July 30, 2018Publication date: February 7, 2019Inventors: Harmeet SOBTI, Mehrdad MANESH, Li-Fu CHANG
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Patent number: 8283377Abstract: Provided is a method for inhibiting blood vessel stenosis in a subject, comprising administrating to the subject an effective amount of an active ingredient selected from a group consisting of a compound of formula (I), a pharmaceutically acceptable salt of the compound, a pharmaceutically acceptable ester of the compound, and combinations thereof. Also provided is a method for inhibiting blood vessel stenosis in a subject, comprising administration to the subject an effective amount of an Angelicae Sinensis extract comprising the compound of formula (I).Type: GrantFiled: May 20, 2011Date of Patent: October 9, 2012Assignee: China Medical UniversityInventors: Shinn-Zong Lin, Horng-Jyh Harn, Tzyy-Wen Chiou, Li-Fu Chang
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Publication number: 20120208875Abstract: Provided is a method for inhibiting blood vessel stenosis in a subject, comprising administrating to the subject an effective amount of an active ingredient selected from a group consisting of a compound of formula (I), a pharmaceutically acceptable salt of the compound, a pharmaceutically acceptable ester of the compound, and combinations thereof. Also provided is a method for inhibiting blood vessel stenosis in a subject, comprising administration to the subject an effective amount of an Angelicae Sinensis extract comprising the compound of formula (I).Type: ApplicationFiled: May 20, 2011Publication date: August 16, 2012Applicant: CHINA MEDICAL UNIVERSITYInventors: Shinn-Zong LIN, Jyh-Harn Horng, Tzyy-Wen Chiou, Li-Fu Chang
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Patent number: 8225248Abstract: DFM systems are provided that incorporate manufacturing variations in the analysis of integrated circuits by calculating predicted manufacturing variations on the shapes of interconnects and devices of the drawn layout of a circuit design. The shape variation on interconnects is converted to variations in resistor-capacitor (RC) parasitics. The shape variation on devices is converted to variations in device parameters. The variation in device parameters and wire parasitics is converted to changes in timing performance, signal integrity, and power consumption by determining the impact of device parameter and wire parasitic variations on the behavior of each instance of a standard cell. The results from these analyses are integrated back into the design flow as incremental delay files (timing), noise failures and buffer insertion/driver resizing commands (noise), and leakage power hotspots and cell substitution commands (power consumption).Type: GrantFiled: October 24, 2006Date of Patent: July 17, 2012Assignee: Cadence Design Systems, Inc.Inventors: Haizhou Chen, Li-Fu Chang, Richard Rouse, Nishath Verghese
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Patent number: 7673260Abstract: DFM systems are provided that incorporate manufacturing variations in the analysis of integrated circuits by calculating predicted manufacturing variations on the shapes of interconnects and devices of the drawn layout of a circuit design. The shape variation on interconnects is converted to variations in resistor-capacitor (RC) parasitics. The shape variation on devices is converted to variations in device parameters. The variation in device parameters and wire parasitics is converted to changes in timing performance, signal integrity, and power consumption by determining the impact of device parameter and wire parasitic variations on the behavior of each instance of a standard cell. The results from these analyses are integrated back into the design flow as incremental delay files (timing), noise failures and buffer insertion/driver resizing commands (noise), and leakage power hotspots and cell substitution commands (power consumption).Type: GrantFiled: October 24, 2006Date of Patent: March 2, 2010Assignee: Cadence Design Systems, Inc.Inventors: Haizhou Chen, Li-Fu Chang, Richard Rouse, Nishath Verghese
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Patent number: 7360191Abstract: Systems and methods for timing-driven shape closure in integrated circuit (“IC”) fabrication are provided. These Integrated Design-Manufacturing Processes (“IDMP”) include a delta flow that integrates information of the IC fabrication timing and geometry verification processes into the IC design. The delta flow is an incremental flow that includes delta-geometry timing prediction processes and/or delta-timing shape prediction processes for processing difference information associated with circuit characterization parameters. The delta flow independently re-characterizes an IC design using the difference or delta information corresponding to the circuit characterization parameters. The delta flow provides delta outputs (incremental) that enhance or re-characterize corresponding parameters of the devices and interconnect structures without the need to generate new circuit characterization parameters and without the need to re-process all information of the IC design.Type: GrantFiled: November 8, 2004Date of Patent: April 15, 2008Assignee: Clear Shape Technologies, Inc.Inventors: Li-Fu Chang, Yao-Ting Wang, Fang-Cheng Chang
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Patent number: 7216320Abstract: Systems and methods for timing-driven shape closure in integrated circuit (“IC”) fabrication are provided. These Integrated Design-Manufacturing Processes (“IDMP”) include a delta flow that integrates information of the IC fabrication timing and geometry verification processes into the IC design. The delta flow is an incremental flow that includes delta-geometry timing prediction processes and/or delta-timing shape prediction processes for processing difference information associated with circuit characterization parameters. The delta flow independently re-characterizes an IC design using the difference or delta information corresponding to the circuit characterization parameters. The delta flow provides delta outputs (incremental) that enhance or re-characterize corresponding parameters of the devices and interconnect structures without the need to generate new circuit characterization parameters and without the need to re-process all information of the IC design.Type: GrantFiled: November 8, 2004Date of Patent: May 8, 2007Assignee: Clear Shape Technologies, Inc.Inventors: Li-Fu Chang, Yao-Ting Wang, Fang-Cheng Chang
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Publication number: 20070099314Abstract: DFM systems are provided that incorporate manufacturing variations in the analysis of integrated circuits by calculating predicted manufacturing variations on the shapes of interconnects and devices of the drawn layout of a circuit design. The shape variation on interconnects is converted to variations in resistor-capacitor (RC) parasitics. The shape variation on devices is converted to variations in device parameters. The variation in device parameters and wire parasitics is converted to changes in timing performance, signal integrity, and power consumption by determining the impact of device parameter and wire parasitic variations on the behavior of each instance of a standard cell. The results from these analyses are integrated back into the design flow as incremental delay files (timing), noise failures and buffer insertion/driver resizing commands (noise), and leakage power hotspots and cell substitution commands (power consumption).Type: ApplicationFiled: October 24, 2006Publication date: May 3, 2007Inventors: Haizhou Chen, Li-Fu Chang, Richard Rouse, Nishath Verghese
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Publication number: 20070094623Abstract: DFM systems are provided that incorporate manufacturing variations in the analysis of integrated circuits by calculating predicted manufacturing variations on the shapes of interconnects and devices of the drawn layout of a circuit design. The shape variation on interconnects is converted to variations in resistor-capacitor (RC) parasitics. The shape variation on devices is converted to variations in device parameters. The variation in device parameters and wire parasitics is converted to changes in timing performance, signal integrity, and power consumption by determining the impact of device parameter and wire parasitic variations on the behavior of each instance of a standard cell. The results from these analyses are integrated back into the design flow as incremental delay files (timing), noise failures and buffer insertion/driver resizing commands (noise), and leakage power hotspots and cell substitution commands (power consumption).Type: ApplicationFiled: October 24, 2006Publication date: April 26, 2007Inventors: Haizhou Chen, Li-Fu Chang, Richard Rouse, Nishath Verghese
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Publication number: 20050172251Abstract: Systems and methods for timing-driven shape closure in integrated circuit (“IC”) fabrication are provided. These Integrated Design-Manufacturing Processes (“IDMP”) include a delta flow that integrates information of the IC fabrication timing and geometry verification processes into the IC design. The delta flow is an incremental flow that includes delta-geometry timing prediction processes and/or delta-timing shape prediction processes for processing difference information associated with circuit characterization parameters. The delta flow independently re-characterizes an IC design using the difference or delta information corresponding to the circuit characterization parameters. The delta flow provides delta outputs (incremental) that enhance or re-characterize corresponding parameters of the devices and interconnect structures without the need to generate new circuit characterization parameters and without the need to re-process all information of the IC design.Type: ApplicationFiled: November 8, 2004Publication date: August 4, 2005Inventors: Li-Fu Chang, Yao-Ting Wang, Fang-Cheng Chang
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Publication number: 20050108666Abstract: Systems and methods for timing-driven shape closure in integrated circuit (“IC”) fabrication are provided. These Integrated Design-Manufacturing Processes (“IDMP”) include a delta flow that integrates information of the IC fabrication timing and geometry verification processes into the IC design. The delta flow is an incremental flow that includes delta-geometry timing prediction processes and/or delta-timing shape prediction processes for processing difference information associated with circuit characterization parameters. The delta flow independently re-characterizes an IC design using the difference or delta information corresponding to the circuit characterization parameters. The delta flow provides delta outputs (incremental) that enhance or re-characterize corresponding parameters of the devices and interconnect structures without the need to generate new circuit characterization parameters and without the need to re-process all information of the IC design.Type: ApplicationFiled: November 8, 2004Publication date: May 19, 2005Inventors: Li-Fu Chang, Yao-Ting Wang, Fang-Cheng Chang
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Patent number: 6643831Abstract: A novel parasitic extraction system includes an interconnect primitive library that has a parameterized inductance function for at least one conducting layer of the integrated circuit. A parasitic extractor analyzes structures within a selected distance of a selected conductor within the integrated circuit and determines parasitic inductance values for the selected conductor using the parameterized inductance function of the interconnect primitive library. Using this parasitic extraction system, parasitic impedances, including inductance, may be extracted for an integrated circuit layout, thus allowing more accurate modeling and timing analysis of the integrated circuit layout to be obtained.Type: GrantFiled: January 24, 2002Date of Patent: November 4, 2003Assignee: Sequence Design, Inc.Inventors: Keh-Jeng Chang, Li-Fu Chang, Robert G. Mathews, Martin G. Walker
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Publication number: 20020104063Abstract: A novel parasitic extraction system includes an interconnect primitive library that has a parameterized inductance function for at least one conducting layer of the integrated circuit. A parasitic extractor analyzes structures within a selected distance of a selected conductor within the integrated circuit and determines parasitic inductance values for the selected conductor using the parameterized inductance function of the interconnect primitive library. Using this parasitic extraction system, parasitic impedances, including inductance, may be extracted for an integrated circuit layout, thus allowing more accurate modeling and timing analysis of the integrated circuit layout to be obtained.Type: ApplicationFiled: January 24, 2002Publication date: August 1, 2002Inventors: Keh-Jeng Chang, Li-Fu Chang, Robert G. Mathews, Martin G. Walker
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Patent number: 6381730Abstract: A novel parasitic extraction system includes an interconnect primitive library that has a parameterized inductance function for at least one conducting layer of the integrated circuit. A parasitic extractor analyzes structures within a selected distance of a selected conductor within the integrated circuit and determines parasitic inductance values for the selected conductor using the parameterized inductance function of the interconnect primitive library. Using this parasitic extraction system, parasitic impedances, including inductance, may be extracted for an integrated circuit layout, thus allowing more accurate modeling and timing analysis of the integrated circuit layout to be obtained.Type: GrantFiled: July 9, 1999Date of Patent: April 30, 2002Assignee: Sequence Design, Inc.Inventors: Keh-Jeng Chang, Li-Fu Chang, Robert G. Mathews, Martin G. Walker
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Patent number: 6311312Abstract: A method models conductive regions of a semiconductor substrate in conjunction with conductors in the interconnect structures above the semiconductor substrate. Such a method allows highly accurate extraction of capacitance in planar (e.g., shallow trench isolation) and non-planar (e.g., thermal oxide isolation) semiconductor structures. This method is particularly applicable to modeling dummy diffusion regions prevalent in shallow trench isolation structures. An area-perimeter approach simplifies calculation of capacitance without using a 3-dimensional electric field solver. A method is also provided for extracting a capacitance associate with a contact, or a connecting conductor between two conductor layers.Type: GrantFiled: September 23, 1999Date of Patent: October 30, 2001Assignee: Sequence Design, Inc.Inventors: Keh-Jeng Chang, Robert G. Mathews, Li-Fu Chang, Xu Yang