Abstract: A method for scaling channel length in a semiconductor device is provided. The method includes increasing a pitch to reduce a development inspection critical dimension (DICD) for a plurality of polysilicon lines. The polysilicon lines are trimmed to provide a reduced-size channel length, based on the reduced DICD, for each polysilicon line. For a particular embodiment, the semiconductor device is fabricated using a photolithography tool having a wavelength of 248 nm, the pitch is about 800 nm, and the reduced-size channel length is about 0.11 ?m.

Abstract: A method for forming a transistor gate includes performing a first exposure of a photo-resist material on a semiconductor device. The first exposure defines a line pattern in the photo-resist material. The method also includes performing a second exposure of the photo-resist material, where the second exposure trims a resist profile of the line pattern. The method further includes etching a conductive material on the semiconductor device to form a transistor gate based on the line pattern. The first exposure could represent a best focus exposure of the photo-resist material, and the second exposure could represent a positive focus exposure of the photo-resist material. The trimming of the line pattern's resist profile may cause the transistor gate to have at least one of a rounded edge and a rounded corner. This may allow a thicker insulating material, such as tetraethylorthosilicate, to be deposited around portions of the transistor gate.

Abstract: A system and method are disclosed for increasing retention reliability of a floating gate of a CMOS compatible memory cell. A mask structure is formed with a plurality of apertures near the edges of the mask structure. The size of the apertures is less than a resolution limitation of a photo exposure system. The mask structure is placed over a resist material and the resist material is exposed to light through the apertures of the mask structure. Zero order diffraction light passes though the apertures and imparts energy to the exposed portions of the resist material. A develop process is then used to remove portions of the resist material to form a sloped edge resist pattern. A sloped edge floating gate that is formed from the pattern facilitates the deposition of a thicker oxide layer at the sloped edge of the floating gate and reduces backend leakage current.

Abstract: A method includes forming a release layer of a semiconductor device being fabricated, where the release layer has a trapezoidal shape. The method also includes forming a cantilever, which has a cantilever arm formed over the release layer. The method further includes removing at least part of the release layer from under the cantilever arm. The release layer could be formed using a photo-resist material. The photo-resist material can be patterned by exposing the photo-resist material using multiple exposures. A first exposure could expose a portion of the photo-resist material, where the exposed portion has substantially vertical sides. A second exposure could give the exposed portion of the photo-resist material slanted sides. A wet etch could be performed to remove the release layer from under the cantilever arm.

Abstract: A semiconductor wafer is disclosed that includes a plurality of fields, including a plurality of alignment fields. Each alignment field includes a plurality of intra-field small scribe lane primary mark (SSPM) overlay mark pairs there around. The SSPM mark pairs allow for in-situ, non-passive intra-field alignment correction. In one embodiment, there may be between two and four alignment fields, and between two and four SSPM mark pairs around each alignment field. The SSPM marks of each mark pair may be extra scribe-lane marks.

Abstract: A semiconductor wafer is disclosed that includes a plurality of fields, including a plurality of alignment fields. Each alignment field includes a plurality of intra-field small scribe lane primary mark (SSPM) overlay mark pairs there around. The SSPM mark pairs allow for in-situ, non-passive intra-field alignment correction. In one embodiment, there may be between two and four alignment fields, and between two and four SSPM mark pairs around each alignment field. The SSPM marks of each mark pair may be extra scribe-lane marks.