Patents by Inventor Li Huang

Li Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240097435
    Abstract: A bypass seamless switching apparatus and a method thereof are provided, in which a controller sends a first control signal to control or switch a first relay to on/off state, sends a second control signal to control or switch a second relay to on/off state, and sends a switch signal to control or switch a bypass switch module to on/off state. When the controller is in failure mode or is disconnected, a driving power supply of a bypass circuit provides a driving signal to the bypass switch module to maintain or switch a switch of the bypass switch module to on state, so that the bypass switch module is in short-circuit state or short-circuit protection state, and a bypass side voltage of the bypass switch module is equal to or close to zero voltage, so as to execute bypass function or bypass seamless switching function of the bypass switch module.
    Type: Application
    Filed: July 6, 2023
    Publication date: March 21, 2024
    Applicant: Industrial Technology Research Institute
    Inventors: Po-Li CHEN, Shu-Syuan HUANG
  • Publication number: 20240093390
    Abstract: The present disclosure relates to an electrode for CO2 electroreduction in an acidic electrolyte comprising cation species, the electrode comprising: a substrate, a metal-based catalyst material, and a cation-augmenting material; wherein the cation-augmenting material comprises an acidic group exchanging protons with the cation species of the acidic electrolyte so as to increase a concentration of the cation species at a surface of the electrode.
    Type: Application
    Filed: March 4, 2022
    Publication date: March 21, 2024
    Inventors: Jianan Erick HUANG, Fengwang LI, Adnan OZDEN, David SINTON, Edward SARGENT
  • Publication number: 20240092584
    Abstract: A conveying device (100) and an inspection system (1000) are provided. The conveying device includes: a first support frame (1); a first conveying mechanism (2) and a second conveying mechanism (3) which are installed on the first support frame; and a switching mechanism (4) configured to selectively lift the first conveying mechanism or the second conveying mechanism in a vertical direction, such that the first conveying mechanism or the second conveying mechanism carries goods (401) and conveys the goods in a first horizontal direction or a second horizontal direction different from the first horizontal direction. The conveying device may achieve a positioning and a smooth continuous conveying of goods, and achieve a smooth conveying and a calibrated positioning of the goods in different postures.
    Type: Application
    Filed: November 22, 2021
    Publication date: March 21, 2024
    Inventors: Li ZHANG, Zhiqiang CHEN, Yuanjing LI, Qingping HUANG, Weijun GUO, Liming YAO, Hui DING, Junhao LIU, Jiajia ZHOU
  • Patent number: 11937300
    Abstract: Methods, apparatuses, and computer readable media for a common preamble for wireless local-area networks (WLANs). An apparatus of an access point (AP) or station (STA) comprising processing circuitry configured to encode an AP trigger frame that includes a resource allocation for other APs to transmit trigger frames to perform an uplink or downlink multi-user transmission with stations (STAs). The resource allocation includes information so that the transmissions are coordinated at the physical level to lessen interference among the APs and the stations. The processing is configured to encode a trigger frame for multi-AP request-to-send (RTS), the multi-AP trigger frame comprising for each of a plurality of APs, the trigger frame indicating that each of a plurality of APs are to transmit a physical (PHY) protocol data unit (PPDU) comprising a request-to-send (RTS) or multi-user (MU) RTS (MU-RTS).
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: March 19, 2024
    Assignee: Intel Corporation
    Inventors: Po-Kai Huang, Qinghua Li, Xiaogang Chen, Robert J. Stacey, Laurent Cariou, Feng Jiang, Yaron Alpert
  • Publication number: 20240088147
    Abstract: An integrated circuit includes a first terminal-conductor, a second terminal-conductor, and a gate-conductor between the first terminal-conductor and the second terminal-conductor. The first terminal-conductor intersects both an active-region structure and a power rail. The second terminal-conductor intersects the active-region structure without intersecting the power rail. The gate-conductor intersects the active-region structure and is adjacent to the first terminal-conductor and the second terminal-conductor. A first width of the first terminal-conductor is larger than a second width of the second terminal-conductor by a predetermined amount.
    Type: Application
    Filed: January 9, 2023
    Publication date: March 14, 2024
    Inventors: XinYong WANG, Cun Cun CHEN, Ying HUANG, Chih-Liang CHEN, Li-Chun TIEN
  • Publication number: 20240088307
    Abstract: A semiconductor package is provided. The semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. The second conductive through-via is in contact with the first conductive through-via. The sensor die is located between the second redistribution structure and the heat dissipation substrate. The second redistribution structure has a window allowing a sensing region of the sensor die receiving light. The first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Yu-Chih Huang, Chih-Hao Chang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
  • Publication number: 20240086026
    Abstract: Systems and methods are disclosed for providing a virtual mouse for a computing device have a touchscreen. A first placement region of the touchscreen may be determined. The first placement region may then be determined to contain a first portion of at least one touch target. The first portion of the at least one touch target may then be deactivated. A virtual mouse may then be activated at the first placement region.
    Type: Application
    Filed: August 15, 2023
    Publication date: March 14, 2024
    Inventors: Roya CODY, Che YAN, Da Yuan HUANG, Wei LI
  • Publication number: 20240087861
    Abstract: In an embodiment, a magnetic assembly includes: an inner permeance annulus; and an outer permeance annulus connected to the inner permeance annulus via magnets, wherein the outer permeance annulus comprises a peak region with a thickness greater than other regions of the outer permeance annulus.
    Type: Application
    Filed: November 17, 2023
    Publication date: March 14, 2024
    Inventors: Tsung-Jen YANG, Yi-Zhen CHEN, Chih-Pin WANG, Chao-Li SHIH, Ching-Hou SU, Cheng-Yi HUANG
  • Patent number: 11925183
    Abstract: The present disclosure relates to a static CT detection device, including: a shielding body, formed with a detection channel through which an object under detection can pass; a ray source, emitting rays for detecting the object under detection when the object under detection passes through the detection channel; and a detector, for acquiring the rays emitted by the ray source and having passed through the detection channel, wherein the shielding body is formed with an opening portion, and the opening portion extends from an inlet of the detection channel to an outlet of the detection channel.
    Type: Grant
    Filed: April 28, 2022
    Date of Patent: March 12, 2024
    Assignees: Tsinghua University, Nuctech Company Limited
    Inventors: Zhiqiang Chen, Li Zhang, Qingping Huang, Yong Zhou, Hui Ding, Chao Ji
  • Patent number: 11929318
    Abstract: A package structure includes a thermal dissipation structure, a first encapsulant, a die, a through integrated fan-out via (TIV), a second encapsulant, and a redistribution layer (RDL) structure. The thermal dissipation structure includes a substrate and a first conductive pad disposed over the substrate. The first encapsulant laterally encapsulates the thermal dissipation structure. The die is disposed on the thermal dissipation structure. The TIV lands on the first conductive pad of the thermal dissipation structure and is laterally aside the die. The second encapsulant laterally encapsulates the die and the TIV. The RDL structure is disposed on the die and the second encapsulant.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Tsung-Hsien Chiang, Yu-Chih Huang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
  • Patent number: 11927555
    Abstract: The design and structure of a fluidic concentration metering device with a full dynamic range utilizing micro-machined thermal time-of-flight sensing elements is exhibited in this disclosure. With an additional identical sensing chip but packaged at the different locations in the measurement fluidic chamber with a closed conduit, the device can simultaneously measure the fluidic concentration and the fluidic flowrate. With a temperature thermistor integrated on the same micro-machined thermal sensing chip, the disclosed device will be able to provide the key processing parameters for the fluidic applications.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: March 12, 2024
    Assignee: Siargo Ltd.
    Inventors: Liji Huang, Yahong Yao, Li Chen, Chih-Chang Chen
  • Publication number: 20240078050
    Abstract: Container data sharing is provided. A second container of a cluster of containers is started to process a service request in response to detecting a failure of a first container processing the service request. The service request and data generated by the first container that failed stored on a physical external memory device is accessed. The service request and the data generated by the first container that failed is loaded on the second container from the physical external memory device via a dedicated hardware link for high-speed container failure recovery.
    Type: Application
    Filed: September 1, 2022
    Publication date: March 7, 2024
    Inventors: Hui Wang, Yue Wang, Mai Zeng, Wei Li, Yu Mei Dai, Xiao Chen Huang
  • Patent number: 11920055
    Abstract: A process for producing a barrier composition includes subjecting a siloxane compound having 1 to 3 amino groups and an aqueous solution including water and an alcohol to hydrolysis and first-stage condensation under required conditions, subjecting a first colloidal mixture obtained and an additional alcohol to second-stage condensation, subjecting a second colloidal mixture obtained, which has a particular solid content, to heating under required conditions, and subjecting a cured product obtained to aging under required conditions. A barrier composition produced by the process is also disclosed.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: March 5, 2024
    Assignee: NATIONAL TAIPEI UNIVERSITY OF TECHNOLOGY
    Inventors: Chung-Kuang Yang, Yi-Hsuan Lai, Sheng-Tung Huang, Kun-Li Wang
  • Patent number: 11923413
    Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate. The semiconductor structure further includes a gate structure surrounding the nanostructures and a source/drain structure attached to the nanostructures. The semiconductor structure further includes a contact formed over the source/drain structure and extending into the source/drain structure.
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-Chun Lin, Kuo-Hua Pan, Jhon-Jhy Liaw, Chao-Ching Cheng, Hung-Li Chiang, Shih-Syuan Huang, Tzu-Chiang Chen, I-Sheng Chen, Sai-Hooi Yeong
  • Patent number: 11921101
    Abstract: Disclosed are calibration techniques that can be implemented by a device that conducts biological tests. In certain embodiments, the device for testing a biological specimen includes a receiving mechanism to receive a carrier, a camera module arranged to capture imagery of the carrier, and a processor. Some examples of the processor can detect a calibration mode trigger. In calibration mode, the processor can divide the captured imagery into segments and selectively perform one or more calibration procedures for each segment. Then, the processor records a calibration result for each segment.
    Type: Grant
    Filed: January 25, 2022
    Date of Patent: March 5, 2024
    Assignee: Bonraybio Co., Ltd.
    Inventors: Cheng-Teng Hsu, Chih-Pin Chang, Kuang-Li Huang, Yu-Chiao Chi, Chia-Wei Chang, Chiung-Han Wang
  • Patent number: 11923201
    Abstract: Semiconductor device structures having metal gate structures with tunable work function values are provided. In one example, a first gate structure and a second gate structure formed on a substrate, wherein the first gate structure includes a first work function metal having a first material, and the second gate structure includes a second work function metal having a second material, the first material being different from the second material, wherein the first gate structure further includes a gate dielectric layer, a self-protective layer having metal phosphate, and the first work function metal on the self-protective layer.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ju-Li Huang, Ying-Liang Chuang, Ming-Hsi Yeh, Kuo-Bin Huang
  • Patent number: 11924866
    Abstract: Embodiments of an Extremely High Throughput Station (EHT STA) (STA1) configured for operating in a next-generation (NG) wireless local area network (WLAN) are described herein. In some embodiments, the EHT STA encodes a common signal field (SIG) (Coex-SIG) of an EHT PPDU to include a TXOP duration field. The TXOP duration field is more than seven bits to indicate an actual TXOP duration of a transmission from the EHT STA comprising the EHT PPDU transmitted to a second station (STA2). Decoding the TXOP duration field of the EHT PPDU by a third-party station (STA4) causes the third-party station (STA4) to defer a transmission until after an end of the transmission from the second station (STA2).
    Type: Grant
    Filed: March 1, 2023
    Date of Patent: March 5, 2024
    Assignee: Intel Corporation
    Inventors: Minyoung Park, Thomas J. Kenney, Laurent Cariou, Po-Kai Huang, Qinghua Li, Xiaogang Chen, Feng Jiang
  • Patent number: 11923352
    Abstract: A semiconductor device is provided. The semiconductor device comprises a first semiconductor die comprising a first capacitor, and a second semiconductor die in contact with the first semiconductor die and comprises a diode. The first semiconductor die and the second semiconductor die are arranged along a first direction, and a diode is configured to direct electrons accumulated at the first capacitor to a ground.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hsin-Li Cheng, Shu-Hui Su, Yu-Chi Chang, Yingkit Felix Tsui, Shih-Fen Huang
  • Patent number: 11923358
    Abstract: A device comprises a first transistor, a second transistor, a first contact, and a second contact. The first transistor comprises a first gate structure, first source/drain regions on opposite sides of the first gate structure, and first gate spacers spacing the first gate structure apart from the first source/drain regions. The second transistor comprises a second gate structure, second source/drain regions on opposite sides of the second gate structure, and second gate spacers spacing the second gate structure apart from the second source/drain regions. The first contact forms a first contact interface with one of the first source/drain regions. The second contact forms a second contact interface with one of the second source/drain regions. An area ratio of the first contact interface to top surface the first source/drain region is greater than an area ratio of the second contact interface to top surface of the second source/drain region.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Pin Huang, Hou-Yu Chen, Chuan-Li Chen, Chih-Kuan Yu, Yao-Ling Huang
  • Patent number: D1017110
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: March 5, 2024
    Assignee: SAVANT TECHNOLOIGES LLC
    Inventors: Zhe Wang, Li Jiang, Jing Chen, Hai Huang, Jie Gao, Kun Xiao, Jiachen Yang