Patents by Inventor Li-Hui Cheng

Li-Hui Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11424174
    Abstract: A method of forming a semiconductor device includes attaching a first semiconductor device to a first surface of a substrate; forming a sacrificial structure on the first surface of the substrate around the first semiconductor device, the sacrificial structure encircling a first region of the first surface of the substrate; and forming an underfill material in the first region.
    Type: Grant
    Filed: October 5, 2020
    Date of Patent: August 23, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Chien Pan, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu
  • Publication number: 20220230985
    Abstract: A jig for manufacturing a semiconductor package includes a bottom piece and an upper piece. The bottom piece includes a base, a support plate, and at least one elastic connector. The support plate is located in a central region of the base. The at least one elastic connector is interposed between the support plate and the base. The upper piece includes a cap and outer flanges. The cap overlays the support plate when the upper piece is disposed on the bottom piece. The outer flanges are disposed at edges of the cap, connected with the cap. The outer flanges contact the base of the bottom piece when the upper piece is disposed on the bottom piece. The cap includes an opening which is a through hole. When the upper piece is disposed on the bottom piece, a vertical projection of the opening falls entirely on the support plate.
    Type: Application
    Filed: January 15, 2021
    Publication date: July 21, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Chen, Chih-Chien Pan, Pu Wang, Li-Hui Cheng, Szu-Wei Lu
  • Publication number: 20220231005
    Abstract: A package structure and methods of forming a package structure are provided. The package structure includes a first die, a second die, a wall structure and an encapsulant. The second die is electrically bonded to the first die. The wall structure is located aside the second die and on the first die. The wall structure is in contact with the first die and a hole is defined within the wall structure for accommodating an optical element. The encapsulant laterally encapsulates the second die and the wall structure.
    Type: Application
    Filed: April 10, 2022
    Publication date: July 21, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chien Pan, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu
  • Patent number: 11393783
    Abstract: A semiconductor device and method utilizing a dummy structure in association with a redistribution layer is provided. By providing the dummy structure adjacent to the redistribution layer, damage to the redistribution layer may be reduced from a patterning of an overlying passivation layer, such as by laser drilling. By reducing or eliminating the damage caused by the patterning, a more effective bond to an overlying structure, such as a package, may be achieved.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: July 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Hui Cheng, Po-Hao Tsai, Jing-Cheng Lin
  • Publication number: 20220223567
    Abstract: A semiconductor package includes a first semiconductor die, an adhesive layer, a second semiconductor die, a plurality of conductive pillars and an encapsulant. The adhesive layer is adhered to the first semiconductor die. The second semiconductor die is stacked over the first semiconductor die. The conductive pillars surround the first semiconductor die.
    Type: Application
    Filed: March 31, 2022
    Publication date: July 14, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Fu Kao, Chih-Yuan Chien, Li-Hui Cheng, Szu-Wei Lu
  • Publication number: 20220157695
    Abstract: Methods of packaging semiconductor devices and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes coupling through-vias to an insulating material, each of the through-vias having a first width. Dies are also coupled to the insulating material. A portion of the insulating material is removed proximate each of the through-vias. The portion of the insulating material proximate each of the through-vias removed has a second width, the second width being less than the first width.
    Type: Application
    Filed: January 31, 2022
    Publication date: May 19, 2022
    Inventors: Li-Hui Cheng, Po-Hao Tsai, Jing-Cheng Lin
  • Publication number: 20220148940
    Abstract: A structure includes a circuit substrate, a device, a metal layer, a lid and a thermal interface material layer. The device is disposed on and electrically connected to the circuit substrate. The device includes at least one semiconductor die laterally encapsulated by an insulating encapsulation. The metal layer is covering a back surface of the at least one semiconductor die and the insulating encapsulation. The lid is disposed on the circuit substrate, and the lid is adhered to the metal layer through the thermal interface material layer.
    Type: Application
    Filed: January 28, 2022
    Publication date: May 12, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Chen, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu
  • Publication number: 20220139802
    Abstract: Provided are a package structure and a method of forming the same. The package structure includes a first die, a second die group, an interposer, an underfill layer, a thermal interface material (TIM), and an adhesive pattern. The first die and the second die group are disposed side by side on the interposer. The underfill layer is disposed between the first die and the second die group. The adhesive pattern at least overlay the underfill layer between the first die and the second die group. The TIM has a bottom surface being in direct contact with the first die, the second die group, and the adhesive pattern. The adhesive pattern separates the underfill layer from the TIM.
    Type: Application
    Filed: January 21, 2022
    Publication date: May 5, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Chen, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu, Chih-Chien Pan
  • Publication number: 20220122922
    Abstract: Semiconductor devices and methods of manufacture are provided, in which an adhesive is removed from a semiconductor die embedded within an encapsulant, and an interface material is utilized to remove heat from the semiconductor device. The removal of the adhesive leaves behind a recess adjacent to a sidewall of the semiconductor, and the recess is filled.
    Type: Application
    Filed: January 15, 2021
    Publication date: April 21, 2022
    Inventors: Chih-Hao Chen, Pu Wang, Li-Hui Cheng, Szu-Wei Lu
  • Publication number: 20220122896
    Abstract: A package structure includes a package substrate, a first semiconductor package and a second semiconductor package, an underfill material, a gap filling structure and a heat dissipation structure. The first semiconductor package and the second semiconductor package are electrically bonded to the package substrate. The underfill material is disposed to fill a first space between the first semiconductor package and the package substrate and a second space between the second semiconductor package and the package substrate. The gap filling structure is disposed over the package substrate and in a first gap laterally between the first semiconductor package and the second semiconductor package. The heat dissipation structure is disposed on the package substrate and attached to the first semiconductor package and the second semiconductor package through a thermal conductive layer.
    Type: Application
    Filed: October 21, 2020
    Publication date: April 21, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pu Wang, Li-Hui Cheng, Szu-Wei Lu, Tsung-Fu Tsai
  • Patent number: 11302683
    Abstract: A package structure and method of forming the same are provided. The package structure includes a first die, a second die, a wall structure and an encapsulant. The second die is electrically bonded to the first die. The wall structure is laterally aside the second die and on the first die. The wall structure is in contact with the first die and a hole is defined within the wall structure for accommodating an optical element insertion. The encapsulant laterally encapsulates the second die and the wall structure.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: April 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chien Pan, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu
  • Patent number: 11296051
    Abstract: Semiconductor packages and methods of forming the same are provided. One of the semiconductor packages includes a first semiconductor die, an adhesive layer, a second semiconductor die and an underfill. The first semiconductor die includes a first surface, and the first surface includes a central region and a peripheral region surrounding the central region. The adhesive layer is adhered to the peripheral region and exposes the central region. The second semiconductor die is stacked over the first surface of the first semiconductor die. The underfill is disposed between the first semiconductor die and the second semiconductor die.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: April 5, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Fu Kao, Chih-Yuan Chien, Li-Hui Cheng, Szu-Wei Lu
  • Publication number: 20220037229
    Abstract: Provided are a package structure and a method of forming the same. The package structure includes a first die, a second die, an interposer, an underfill layer, a thermal interface material (TIM), and an adhesive pattern. The first die and the second die are disposed side by side on the interposer. The underfill layer is disposed between the first die and the second die. The TIM is disposed on the first die, the second die, and the underfill layer. The adhesive pattern is disposed between the underfill layer and the TIM to separate the underfill layer from the TIM.
    Type: Application
    Filed: July 28, 2020
    Publication date: February 3, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hao Chen, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu, Chih-Chien Pan
  • Patent number: 11239136
    Abstract: Provided are a package structure and a method of forming the same. The package structure includes a first die, a second die, an interposer, an underfill layer, a thermal interface material (TIM), and an adhesive pattern. The first die and the second die are disposed side by side on the interposer. The underfill layer is disposed between the first die and the second die. The TIM is disposed on the first die, the second die, and the underfill layer. The adhesive pattern is disposed between the underfill layer and the TIM to separate the underfill layer from the TIM.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: February 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Chen, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu, Chih-Chien Pan
  • Patent number: 11239138
    Abstract: Methods of packaging semiconductor devices and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes coupling through-vias to an insulating material, each of the through-vias having a first width. Dies are also coupled to the insulating material. A portion of the insulating material is removed proximate each of the through-vias. The portion of the insulating material proximate each of the through-vias removed has a second width, the second width being less than the first width.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: February 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Li-Hui Cheng, Po-Hao Tsai, Jing-Cheng Lin
  • Patent number: 11239134
    Abstract: A structure includes a circuit substrate, a device, a metal layer, a lid and a thermal interface material layer. The device is disposed on and electrically connected to the circuit substrate. The device includes at least one semiconductor die laterally encapsulated by an insulating encapsulation. The metal layer is covering a back surface of the at least one semiconductor die and the insulating encapsulation. The lid is disposed on the circuit substrate, and the lid is adhered to the metal layer through the thermal interface material layer.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: February 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Chen, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu
  • Patent number: 11205612
    Abstract: In an embodiment, a package includes: an interposer having a first side; a first integrated circuit device attached to the first side of the interposer; a second integrated circuit device attached to the first side of the interposer; an underfill disposed beneath the first integrated circuit device and the second integrated circuit device; and an encapsulant disposed around the first integrated circuit device and the second integrated circuit device, a first portion of the encapsulant extending through the underfill, the first portion of the encapsulant physically disposed between the first integrated circuit device and the second integrated circuit device, the first portion of the encapsulant being planar with edges of the underfill and edges of the first and second integrated circuit devices.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: December 21, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chien Pan, Li-Hui Cheng, Chin-Fu Kao, Szu-Wei Lu
  • Publication number: 20210358768
    Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a semiconductor die, conductive through vias, an insulating encapsulant, and a redistribution structure. The conductive through vias are electrically coupled to the semiconductor die. The insulating encapsulant laterally encapsulates the semiconductor die and the conductive through vias, wherein the insulating encapsulant has a recess ring surrounding the semiconductor die, the conductive through vias are located under the recess ring, and a vertical projection of each of the conductive through vias overlaps with a vertical projection of the recess ring. The redistribution structure is electrically connected to the semiconductor die and the conductive through vias.
    Type: Application
    Filed: July 29, 2021
    Publication date: November 18, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Hui Cheng, Szu-Wei Lu, Ping-Yin Hsieh, Chih-Hao Chen
  • Publication number: 20210343611
    Abstract: A method for forming a package structure is provided. The method for forming a package structure includes bonding a package component to a first surface of a substrate through a plurality of first connectors. The package component includes a first semiconductor die and a second semiconductor die. The method also includes forming a dam structure over the first surface of the substrate. The dam structure is around and separated from the package component, and a top surface of the dam structure is higher than a top surface of the package component. The method further includes forming an underfill layer between the dam structure and the package component. In addition, the method includes removing the dam structure after the underfill layer is formed.
    Type: Application
    Filed: July 12, 2021
    Publication date: November 4, 2021
    Inventors: Chih-Hao CHEN, Chih-Chien PAN, Li-Hui CHENG, Chin-Fu KAO, Szu-Wei LU
  • Publication number: 20210313304
    Abstract: A package structure and method of forming the same are provided. The package structure includes a first die, a second die, a wall structure and an encapsulant. The second die is electrically bonded to the first die. The wall structure is laterally aside the second die and on the first die. The wall structure is in contact with the first die and a hole is defined within the wall structure for accommodating an optical element insertion. The encapsulant laterally encapsulates the second die and the wall structure.
    Type: Application
    Filed: April 1, 2020
    Publication date: October 7, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chien Pan, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu