Patents by Inventor Li-Ken Yeh
Li-Ken Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11699683Abstract: A semiconductor device with an interface includes a master device and a plurality of slave devices. The master device includes a master interface. The slave devices are stacked on the master device one after one as a three-dimension (3D) stack. Each of the slave devices includes a slave interface and a managing circuit, the master interface and the slave interfaces form the interface for passing signals in communication between the master device and the slave devices. The managing circuit of a current one of the slave devices drives a next one of the slave devices. An operation command received at the current one of the slave devices is just passed to the next one of the slave devices through the interface. A response from the current one of the slave devices is passed back to the master device through the interface.Type: GrantFiled: September 30, 2020Date of Patent: July 11, 2023Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Igor Elkanovich, Amnon Parnass, Pei Yu, Li-Ken Yeh, Yung-Sheng Fang, Sheng-Wei Lin, Tze-Chiang Huang, King Ho Tam, Ching-Fang Chen
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Patent number: 11687472Abstract: An interface for a semiconductor device is provided. The semiconductor device has a master device and multiple slave devices as stacked up with electric connection. The interface includes a master interface, implemented in the master device and including a master interface circuit with a master bond pattern. Further, a slave interface is implemented in each slave device and includes a slave interface circuit with a slave bond pattern to correspondingly connect to the master bond pattern. A clock route is to transmit a clock signal through the master interface and the slave interface. The master device transmits a command and a selecting slave identification through the master interface to all the slave interfaces. One of the slave devices corresponding to the selecting slave identification executes the command and responds a result back to the master device through the slave interfaces and the master interface.Type: GrantFiled: August 20, 2020Date of Patent: June 27, 2023Assignees: GLOBAL UNICHIP CORPORATION, Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Igor Elkanovich, Amnon Parnass, Pei Yu, Li-Ken Yeh, Yung-Sheng Fang, Sheng-Wei Lin, Tze-Chiang Huang, King Ho Tam, Ching-Fang Chen
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Patent number: 11675731Abstract: A data protection system and a data protection method for handling an errored command are provided. The data protection system includes a master device and a slave device. The master device is configured to send command. The slave device is coupled to the master device. The save device is configured to receive the command from the master device. The master device includes a master interface. The slave device includes a slave interface. The master interface and the slave interface are electrically connected via one or plurality of bonds and/or TSVs and configured for interfacing between the master device and the slave device. The errored command represents the command having a parity or other error. The slave device is further configured to receive the errored command and to respond the errored command according to read or write operation.Type: GrantFiled: September 30, 2020Date of Patent: June 13, 2023Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Igor Elkanovich, Amnon Parnass, Pei Yu, Li-Ken Yeh, Yung-Sheng Fang, Sheng-Wei Lin, Tze-Chiang Huang, King Ho Tam, Ching-Fang Chen
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Patent number: 11515278Abstract: A communication interface structure for connection between dies is provided, including a memory die, processing dies and interconnection routings. The memory die includes a first interface edge, wherein the first interface edge is split into a plurality of interface groups. Each of the processing dies includes a second interface edge. Interconnection routings respectively connect the second interface edges of the processing dies to the interface groups of the memory die.Type: GrantFiled: February 25, 2021Date of Patent: November 29, 2022Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Chieh Liao, Igor Elkanovich, Hung-Yi Chang, Li-Ken Yeh, Chung-Ling Liou
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Publication number: 20220270996Abstract: A communication interface structure for connection between dies is provided, including a memory die, processing dies and interconnection routings. The memory die includes a first interface edge, wherein the first interface edge is split into a plurality of interface groups. Each of the processing dies includes a second interface edge. Interconnection routings respectively connect the second interface edges of the processing dies to the interface groups of the memory die.Type: ApplicationFiled: February 25, 2021Publication date: August 25, 2022Applicants: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Chieh Liao, Igor Elkanovich, Hung-Yi Chang, Li-Ken Yeh, Chung-Ling Liou
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Publication number: 20220058155Abstract: A data protection system and a data protection method for handling an errored command are provided. The data protection system includes a master device and a slave device. The master device is configured to send command. The slave device is coupled to the master device. The save device is configured to receive the command from the master device. The master device includes a master interface. The slave device includes a slave interface. The master interface and the slave interface are electrically connected via one or plurality of bonds and/or TSVs and configured for interfacing between the master device and the slave device. The errored command represents the command having a parity or other error. The slave device is further configured to receive the errored command and to respond the errored command according to read or write operation.Type: ApplicationFiled: September 30, 2020Publication date: February 24, 2022Applicants: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Igor Elkanovich, Amnon Parnass, Pei Yu, Li-Ken Yeh, Yung-Sheng Fang, Sheng-Wei Lin, Tze-Chiang Huang, King Ho Tam, Ching-Fang Chen
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Publication number: 20220058144Abstract: An interface for a semiconductor device is provided. The semiconductor device has a master device and multiple slave devices as stacked up with electric connection. The interface includes a master interface, implemented in the master device and including a master interface circuit with a master bond pattern. Further, a slave interface is implemented in each slave device and includes a slave interface circuit with a slave bond pattern to correspondingly connect to the master bond pattern. A clock route is to transmit a clock signal through the master interface and the slave interface. The master device transmits a command and a selecting slave identification through the master interface to all the slave interfaces. One of the slave devices corresponding to the selecting slave identification executes the command and responds a result back to the master device through the slave interfaces and the master interface.Type: ApplicationFiled: August 20, 2020Publication date: February 24, 2022Applicants: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Igor Elkanovich, Amnon Parnass, Pei Yu, Li-Ken Yeh, Yung-Sheng Fang, Sheng-Wei Lin, Tze-Chiang Huang, King Ho Tam, Ching-Fang Chen
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Publication number: 20220059501Abstract: A semiconductor device with an interface includes a master device and a plurality of slave devices. The master device includes a master interface. The slave devices are stacked on the master device one after one as a three-dimension (3D) stack. Each of the slave devices includes a slave interface and a managing circuit, the master interface and the slave interfaces form the interface for passing signals in communication between the master device and the slave devices. The managing circuit of a current one of the slave devices drives a next one of the slave devices. An operation command received at the current one of the slave devices is just passed to the next one of the slave devices through the interface. A response from the current one of the slave devices is passed back to the master device through the interface.Type: ApplicationFiled: September 30, 2020Publication date: February 24, 2022Applicants: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Igor Elkanovich, Amnon Parnass, Pei Yu, Li-Ken Yeh, Yung-Sheng Fang, Sheng-Wei Lin, Tze-Chiang Huang, King Ho Tam, Ching-Fang Chen
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Patent number: 11144485Abstract: An interface for a semiconductor device includes a master device and a plurality of slave devices. The interface includes a master interface and a slave interface. The master interface is implemented in the master device and includes a master bond pattern of master bonds arranged as a first array. The slave interface is implemented each slave device and includes a slave bond pattern of slave bonds arranged as a second array. The first array of the master bonds includes a first central row and first data rows in two parts being symmetric to the first central row. The second array of the slave bonds includes a second central row and second data rows in two parts being symmetric to the second central row. The first central row and the second central row are aligned in connection, and the first data rows are connected to the second data rows.Type: GrantFiled: September 30, 2020Date of Patent: October 12, 2021Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Igor Elkanovich, Amnon Parnass, Pei Yu, Li-Ken Yeh, Yung-Sheng Fang, Sheng-Wei Lin, Tze-Chiang Huang, King Ho Tam, Ching-Fang Chen
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Patent number: 11031923Abstract: An interface device and an interface method for interfacing between a master device and a slave device is provided. The master device generates command and the slave device generates data according to the command. The interface device includes a master interface and a slave interface. The master interface is coupled to the master device and configured to send the command to the slave device and/or receive the data from the slave device. The slave interface is coupled to the slave device and configured to receive the command from the master device and/or send the data to the master device. The master interface and the slave interface are driven by a clock generated by a clock generator. The master interface and the slave interface are electrically connected by one or plurality of bonds and/or TSVs.Type: GrantFiled: September 30, 2020Date of Patent: June 8, 2021Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Igor Elkanovich, Amnon Parnass, Pei Yu, Li-Ken Yeh, Yung-Sheng Fang, Sheng-Wei Lin, Tze-Chiang Huang, King Ho Tam, Ching-Fang Chen
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Patent number: 8476910Abstract: A capacitive sensor with a calibration mechanism is provided. The capacitive sensor includes a set of sensing capacitors to generate a capacitance variation, a subtraction circuit and an integration circuit. The subtraction circuit includes a first capacitor array to generate offset-adjusting charges and a second capacitor array to generate subtraction charges according to an initial offset and a sensitivity of the sensing capacitors respectively. The integration circuit includes two input ends, wherein one of them is connected to the sensing capacitors and the subtraction circuit. During a sensing period, the integration circuit performs integration according to the capacitance variation and performs cancellation of the effect of the initial offset according to the offset-adjusting charges to generate an integration output signal that is continuously subtracted by the subtraction charges during a computing period to generate a subtraction count. A capacitive sensing method is disclosed herein as well.Type: GrantFiled: June 23, 2010Date of Patent: July 2, 2013Assignee: Memsor CorporationInventors: Li-Ken Yeh, Siew-Seong Tan
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Publication number: 20110248723Abstract: A capacitive sensor with a calibration mechanism is provided. The capacitive sensor includes a set of sensing capacitors to generate a capacitance variation, a subtraction circuit and an integration circuit. The subtraction circuit includes a first capacitor array to generate offset-adjusting charges and a second capacitor array to generate subtraction charges according to an initial offset and a sensitivity of the sensing capacitors respectively. The integration circuit includes two input ends, wherein one of them is connected to the sensing capacitors and the subtraction circuit. During a sensing period, the integration circuit performs integration according to the capacitance variation and performs cancellation of the effect of the initial offset according to the offset-adjusting charges to generate an integration output signal that is continuously subtracted by the subtraction charges during a computing period to generate a subtraction count. A capacitive sensing method is disclosed herein as well.Type: ApplicationFiled: June 23, 2010Publication date: October 13, 2011Applicant: MEMSOR CORPORATIONInventors: Li-Ken YEH, Siew-Seong TAN
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Patent number: 7935556Abstract: A micro electromechanical system and a fabrication method thereof, which has trenches formed on a substrate to prevent circuits from interfering each other, and to prevent over-etching of the substrate when releasing a microstructure.Type: GrantFiled: August 27, 2007Date of Patent: May 3, 2011Assignee: Memsmart Semiconductor Corp.Inventors: Li-Ken Yeh, I-Hsiang Chiu
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Publication number: 20100109121Abstract: A micro electromechanical system and a fabrication method thereof, which has trenches formed on a substrate to prevent circuits from interfering each other, and to prevent over-etching of the substrate when releasing a microstructure.Type: ApplicationFiled: January 5, 2010Publication date: May 6, 2010Applicant: MEMSMART SEMICONDUCTOR CORP.Inventors: Li-Ken YEH, I-Hsiang CHIU
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Patent number: 7666702Abstract: A method for fabricating a microstructure is to form at least one insulation layer including a micro-electro-mechanical structure therein over an upper surface of a silicon substrate. The micro-electro-mechanical structure includes at least one microstructure and a metal sacrificial structure that are independent with each other. In the metal sacrificial structure are formed a plurality of metal layers and a plurality of metal via layers connected to the respective metal layers. A barrier layer is formed over an upper surface of the insulation layer, and an etching stop layer is subsequently formed over a lower surface of the silicon substrate. An etching operation is carried out from the lower surface of the silicon substrate to form a space corresponding to the micro-electro-mechanical structure, and then the metal sacrificial structure is etched, thus achieving a microstructure suspension.Type: GrantFiled: November 28, 2007Date of Patent: February 23, 2010Assignee: MEMSmart Semiconductor Corp.Inventors: Sheng-Hung Li, Siew-Seong Tan, Cheng-Yen Liu, Li-Ken Yeh
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Publication number: 20090137113Abstract: A method for fabricating a microstructure is to form at least one insulation layer including a micro-electro-mechanical structure therein over an upper surface of a silicon substrate. The micro-electro-mechanical structure includes at least one microstructure and a metal sacrificial structure that are independent with each other. In the metal sacrificial structure are formed a plurality of metal layers and a plurality of metal via layers connected to the respective metal layers. A barrier layer is formed over an upper surface of the insulation layer, and an etching stop layer is subsequently formed over a lower surface of the silicon substrate. An etching operation is carried out from the lower surface of the silicon substrate to form a space corresponding to the micro-electro-mechanical structure, and then the metal sacrificial structure is etched, thus achieving a microstructure suspension.Type: ApplicationFiled: November 28, 2007Publication date: May 28, 2009Inventors: Sheng Hung Li, Siew-Seong Tan, Cheng-Yen Liu, Li-Ken Yeh
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Publication number: 20090057817Abstract: A micro electromechanical system and a fabrication method thereof, which has trenches formed on a substrate to prevent circuits from interfering each other, and to prevent over-etching of the substrate when releasing a microstructure.Type: ApplicationFiled: August 27, 2007Publication date: March 5, 2009Inventors: Li-Ken YEH, I-Hsiang CHIU