Patents by Inventor Li Liang
Li Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11987014Abstract: This invention disclosed a resin-based composite material has a three-layer structure and the application thereof. According to the invention, an oriented carbon nanotube bundle/epoxy resin composite material (denoted as layer B) is prepared with the microwave curing method, a barium titanate nanofiber/epoxy resin composite material (denoted as layer E) is prepared by means of a blade coating-heat curing method, and a composite material of a B-E-B three layer structural is formed by means of a layer-by-layer curing technology. Compared to the composite material of the conductor-insulating layer/polymer layer structural prepared in the prior art, the resin-based composite material has a three-layer structure provided by the invention has with high energy storage density, and low dielectric loss and high permittivity; and the preparation process therefor is controllable and easy to operate, short in production cycle, and suitable for large-scale application.Type: GrantFiled: January 15, 2019Date of Patent: May 21, 2024Assignee: SOOCHOW UNIVERSITYInventors: Aijuan Gu, Guozheng Liang, Li Yuan
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Publication number: 20240157437Abstract: A method produces tantalum powder. The method includes: (1) uniformly mixing a tantalum powder raw material, metal magnesium and at least one alkali metal and/or alkaline earth metal halide, loading the mixture into a container, and putting the container in a furnace; (2) raising the temperature of the furnace to 600-1200° C. in the presence of inert gas, and soaking; (3) at the end of soaking, lowering the temperature of the furnace to 600-800° C., vacuumizing the interior of the furnace to 10 Pa or less, soaking under the negative pressure so that the excessive metal is separated; (4) thereafter, raising the temperature of the furnace to 750-1200° C. in the presence of inert gas, and soaking so that the tantalum powder is sintered in the molten salt after oxygen reduction; (5) then cooling to room temperature and passivating to obtain a mixed material containing halide and tantalum powder; and (6) separating the tantalum powder from the resulting mixture.Type: ApplicationFiled: August 24, 2022Publication date: May 16, 2024Inventors: Yuewei Cheng, Hongyuan Liang, Shun Guo, Jinfeng Zheng, Haiyan Ma, Jingyi Zuo, Li Zhang, Hongjie Qin, Tong Liu, Ying Wang
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Publication number: 20240156293Abstract: A radiographic inspection device and a method of inspecting an object are provided. The radiographic inspection device includes: a support frame, where an inspection space applicable to inspect an object is formed within the support frame, and the inspection space has an entrance and an exit which are connecting to an outside; a transfer channel applicable to carry the object to move through the inspection space; a first shielding curtain and a second shielding curtain respectively mounted at the entrance and the exit; and a driving mechanism mounted on the support frame and configured to drive at least one of the first shielding curtain and the second shielding curtain to move, in response to the object getting close to or moving away from at least one of the entrance and the exit, so as to open or close the at least one of the entrance or the exit.Type: ApplicationFiled: January 11, 2022Publication date: May 16, 2024Inventors: Li ZHANG, Zhiqiang CHEN, Qingping HUANG, Jinning LIANG, Mingzhi HONG, Yi CHENG, Minghua QIU, Yao ZHANG, Jianxue YANG, Lei ZHENG
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Patent number: 11981783Abstract: A method for preparing a transparent flexible polyurethane film includes the following steps: (1) mixing a hydroxyl-terminated polyalkylene carbonate diol, a diisocyanate compound, 2,2?-dithiodiethanol, dibutyltin dilaurate and a chloroalkane solvent, and then reacting at 40 to 60° C. for 0.5 to 3 h to obtain an isocyanate-terminated oligomer solution; and (2) adding a polyol cross-linking agent, a bistrifluoromethanesulfonimide lithium salt and a 1-ethyl-3-methylimidazole bistrifluoromethanesulfonimide salt to the isocyanate-terminated oligomer solution, reacting at 40 to 60° C. for 0.5 to 1.5 h, removing the chloroalkane solvent to obtain the transparent flexible polyurethane film.Type: GrantFiled: August 10, 2021Date of Patent: May 14, 2024Assignee: SOOCHOW UNIVERSITYInventors: Aijuan Gu, Guozheng Liang, Li Yuan
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Publication number: 20240150469Abstract: Provided herein are methods of treating B7-H1-expressing tumors comprising administering an effective amount of MEDI4736 or an antigen-binding fragment thereof.Type: ApplicationFiled: October 20, 2023Publication date: May 9, 2024Inventors: Rajest Narwal, David Fairman, Paul Robbins, Meina Liang, Amy Schneider, Carlos Chavez, Carina Herl, Min Pak, Hong Lu, Marlon Rebelatto, Keith Steele, AnnMarie Boutrin, Li Shi, SHENGYAN HONG, Brandon Higgs, Lorin Roskos
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Publication number: 20240150194Abstract: A low-carbon, high-purity tantalum pentoxide powder has a carbon content of no greater than 15 ppm. A preparation method for the powder includes: (1) adding a fluotantalic acid (H2TaF7) solution into a reaction kettle, controlling the temperature of the reaction kettle at 30-60° C., adding a precipitator until the pH of the reaction solution is 8-10, then stopping introducing ammonia, and aging to obtain a tantalum hydroxide slurry; (2) filtering and washing the slurry obtained in step (1), and then carrying out solid-liquid separation to obtain a tantalum hydroxide filter cake; (3) drying the filter cake obtained in step (2) to obtain white tantalum hydroxide powder; (4) calcining the tantalum hydroxide powder obtained in step (3), crushing and screening the calcined sample to obtain tantalum pentoxide powder; and (5) subjecting the tantalum pentoxide powder obtained in step (4) to heat treatment at a temperature of 1000-1500° C. to obtain the powder.Type: ApplicationFiled: August 24, 2022Publication date: May 9, 2024Applicant: NINGXIA ORIENT TANTALUM INDUSTRY CO., LTD.Inventors: Shun Guo, Jinfeng Zheng, Tao Guo, Hongyuan Liang, Yuewei Cheng, Jingyi Zuo, Li Zhang, Ying Wang, Tong Liu, Hongjie Qin
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Publication number: 20240153942Abstract: An integrated circuit is provided and includes a multi-bit cell having multiple bit cells disposed in multiple cell rows. The bit cells include M bit cells, M being positive integers. A first bit cell of the bit cells and a M-th bit cell of the bit cells are arranged diagonally in different cell rows in the multi-bit cell. The multi-bit cell includes first to fourth cell boundaries. The first and second boundaries extend in a first direction and the third and fourth boundaries extend in a second direction different from the first direction. The first bit cell and a second bit cell of the bit cells abut the third cell boundary, and the first bit cell and a (M/2+1)-th bit cell of the bit cells abut the first cell boundary.Type: ApplicationFiled: January 17, 2024Publication date: May 9, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shao-Lun CHIEN, Po-Chun WANG, Hui-Zhong ZHUANG, Chih-Liang CHEN, Li-Chun TIEN
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Patent number: 11974844Abstract: Electrochemical impedance spectroscopy (EIS) may be used in conjunction with continuous glucose monitoring (CGM) to enable identification of valid and reliable sensor data, as well implementation of Smart Calibration algorithms.Type: GrantFiled: April 29, 2019Date of Patent: May 7, 2024Assignee: MEDTRONIC MINIMED, INC.Inventors: Keith Nogueira, Taly G. Engel, Xiaolong Li, Bradley C. Liang, Rajiv Shah, Jaeho Kim, Mike C. Liu, Andy Y. Tsai
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Patent number: 11978751Abstract: An electrode controls transmittance of a blocking layer over a photodiode of a pixel sensor (e.g., a photodiode of a small pixel detector) by changing oxidation of a metal material included in the blocking layer. By using the electrode to adjust transmittance of the blocking layer, pixel sensors for different uses and/or products may be produced using a single manufacturing process. As a result, power and processing resources are conserved that otherwise would have been expended in switching manufacturing processes. Additionally, production time is decreased (e.g., by eliminating downtime that would otherwise have been used to reconfigure fabrication machines.Type: GrantFiled: January 10, 2023Date of Patent: May 7, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Wen Huang, Chung-Liang Cheng, Ping-Hao Lin, Kuo-Cheng Lee
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Patent number: 11977523Abstract: Embodiments of the present invention are directed to facilitating performing data extraction via efficient extraction rule matching. Generally, an extraction rule can be determined to match an event based on a two-step process. In particular, initially, a determination that a set of fixed substrings associated with the extraction rule matches fixed substrings of the event can be made. Based on fixed substring match, a determination can be made that a set of fields associated with the extraction rule matches fields of the event. In such a case, the extraction rule can be deemed to match the event and used to extract values from the event.Type: GrantFiled: April 27, 2020Date of Patent: May 7, 2024Assignee: Splunk Inc.Inventors: Li Li, Zi Liang Chen, Gang Tao, Dinesh Sharma, Alex Cain
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Publication number: 20240145481Abstract: A semiconductor structure includes a first transistor, a second transistor, a first dummy source/drain, a third transistor, a fourth transistor, and a second dummy source/drain. The first transistor and a second transistor adjacent to the first transistor are at a first elevation. The first dummy source/drain is disposed at the first elevation. The third transistor and a fourth transistor adjacent to the third transistor, are at a second elevation different from the first elevation. The second dummy source/drain is disposed at the second elevation. The second transistor is vertically aligned with the third transistor. The first dummy source/drain is vertically aligned with a source/drain of the fourth transistor. The second dummy source/drain is vertically aligned with a source/drain of the first transistor. The gate structure between the second dummy source/drain and a source/drain of the third transistor is absent. A method for manufacturing a semiconductor structure is also provided.Type: ApplicationFiled: January 4, 2024Publication date: May 2, 2024Inventors: POCHUN WANG, GUO-HUEI WU, HUI-ZHONG ZHUANG, CHIH-LIANG CHEN, LI-CHUN TIEN
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Publication number: 20240147685Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first source/drain (S/D) epitaxial feature disposed over a substrate, a second S/D epitaxial feature adjacent the first S/D epitaxial feature, and a hybrid fin disposed between the first and second S/D epitaxial features. The hybrid fin includes a first dielectric material, a second dielectric material disposed on the first dielectric material, a dielectric layer surrounding the first and second dielectric materials, and a high-k dielectric layer disposed in the first and second dielectric materials. The high-k dielectric layer has an upper surface located at a level between a level of an upper surface of the second dielectric material and a level of a lower surface of the second dielectric material.Type: ApplicationFiled: January 19, 2023Publication date: May 2, 2024Inventors: Wen-Li Chiu, Chun-Sheng Liang
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Patent number: 11972974Abstract: An IC structure includes a transistor, a source/drain contact, a metal oxide layer, a non-metal oxide layer, a barrier structure, and a via. The transistor includes a gate structure and source/drain regions on opposite sides of the gate structure. The source/drain contact is over one of the source/drain regions. The metal oxide layer is over the source/drain contact. The non-metal oxide layer is over the metal oxide layer. The barrier structure is over the source/drain contact. The barrier structure forms a first interface with the metal oxide layer and a second interface with the non-metal oxide layer, and the second interface is laterally offset from the first interface. The via extends through the non-metal oxide layer to the barrier structure.Type: GrantFiled: January 13, 2022Date of Patent: April 30, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Sung-Li Wang, Shuen-Shin Liang, Yu-Yun Peng, Fang-Wei Lee, Chia-Hung Chu, Mrunal Abhijith Khaderbad, Keng-Chu Lin
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Publication number: 20240132078Abstract: A driving model training method, a driver identification method, an apparatus, a device and a medium are provided. The training method comprises: acquiring training behavior data of a user wherein the training behavior data are associated with a user identifier; acquiring training driving data associated with the user identifier based on the training behavior data; acquiring positive and negative samples from the training driving data based on the user identifier, and dividing the positive and negative samples into a training set and a test set; training the training set using a bagging algorithm, and acquiring an original driving model; testing the original driving model using the test set, and acquiring a target driving model. The training method effectively enhances generalization of the driving model, solves the problem of poor identification results of the existing driving identification model, and improves the accuracy rate of identifying driving of drivers.Type: ApplicationFiled: December 25, 2023Publication date: April 25, 2024Inventors: Xin Jin, Zhuangwei Wu, Chuan Zhang, Yuanyuan Zhao, Duxin Huang, Yongjian Liang, Li Huo
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Patent number: 11967596Abstract: An integrated circuit includes a first-voltage power rail and a second-voltage power rail in a first connection layer, and includes a first-voltage underlayer power rail and a second-voltage underlayer power rail below the first connection layer. Each of the first-voltage and second-voltage power rails extends in a second direction that is perpendicular to a first direction. Each of the first-voltage and second-voltage underlayer power rails extends in the first direction. The integrated circuit includes a first via-connector connecting the first-voltage power rail with the first-voltage underlayer power rail, and a second via-connector connecting the second-voltage power rail with the second-voltage underlayer power rail.Type: GrantFiled: August 5, 2021Date of Patent: April 23, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Guo-Huei Wu, Shih-Wei Peng, Wei-Cheng Lin, Hui-Zhong Zhuang, Chih-Liang Chen, Li-Chun Tien, Lee-Chung Lu
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Patent number: 11953926Abstract: Voltage regulation schemes for powering multiple circuit blocks are disclosed. In certain embodiments, a front end system includes a reference voltage circuit that receives power from a power supply voltage and generates a reference voltage, a group of circuit blocks each selectively enabled by a corresponding one of a group of enable signals, and a programmable voltage regulator that generates a programmable regulated voltage based on the reference voltage and provides the programmable regulated voltage to the circuit blocks. The programmable regulated voltage has a voltage level that changes based on a selection of the circuit blocks that are enabled by the enable signals.Type: GrantFiled: June 16, 2022Date of Patent: April 9, 2024Assignee: Skyworks Solutions, Inc.Inventors: Bang Li Liang, Guillaume Alexandre Blin, Thomas Obkircher
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Patent number: 11948886Abstract: A semiconductor device includes one or more active semiconductor components, wherein a front side is defined over the semiconductor substrate and a back side is defined beneath the semiconductor substrate. A front side power rail is formed at the front side of the semiconductor device and is configured to receive a first reference power voltage. First and second back side power rails are formed on the back side of the semiconductor substrate and are configured to receive corresponding second and third reference power voltages. The first, second and third reference power voltages are different from each other.Type: GrantFiled: April 29, 2021Date of Patent: April 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Guo-Huei Wu, Hui-Zhong Zhuang, Chih-Liang Chen, Li-Chun Tien
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Patent number: 11948954Abstract: An electrode controls transmittance of a blocking layer over a photodiode of a pixel sensor (e.g., a photodiode of a small pixel detector) by changing oxidation of a metal material included in the blocking layer. By using the electrode to adjust transmittance of the blocking layer, pixel sensors for different uses and/or products may be produced using a single manufacturing process. As a result, power and processing resources are conserved that otherwise would have been expended in switching manufacturing processes. Additionally, production time is decreased (e.g., by eliminating downtime that would otherwise have been used to reconfigure fabrication machines.Type: GrantFiled: January 10, 2023Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Wen Huang, Chung-Liang Cheng, Ping-Hao Lin, Kuo-Cheng Lee
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Publication number: 20240101602Abstract: Provided is a peptide and method in preventing or treating infections caused by a wide spectrum of pathogens, including bacteria and fungus in hosts such as plants and animals. Methods of preventing or treating plant diseases and infection in animals are also provided.Type: ApplicationFiled: November 24, 2021Publication date: March 28, 2024Inventors: Rita P.Y. Chen, Chiu-Ping CHENG, Chien-Chih YANG, Kung-Ta LEE, Ying-Lien CHEN, Li-Hang Hsu, Hsin-Liang CHEN, Sung CHEN
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Publication number: 20240105848Abstract: A semiconductor device structure is provided. The semiconductor device structure includes multiple semiconductor nanostructures, and the semiconductor nanostructures include a first semiconductor material. The semiconductor device structure also includes multiple epitaxial structures extending from edges of the semiconductor nanostructures. The epitaxial structures include a second semiconductor material that is different than the first semiconductor material. The semiconductor device structure further includes a gate stack wrapped around the semiconductor nanostructures.Type: ApplicationFiled: November 29, 2023Publication date: March 28, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shuen-Shin LIANG, Pang-Yen TSAI, Keng-Chu LIN, Sung-Li WANG, Pinyen LIN