Abstract: Protection of a kernel from a sniff and code reuse attack. A kernel mode page table in initialized in a kernel. The kernel page entries in the kernel mode page table are set from s-pages to u-pages. Supervisor mode access prevention is enabled in the u-pages. Code contained in the kernel page entries in the u-pages is executed, the kernel page entries in the u-pages are capable of execution but are not capable of being accessed and read directly.

Abstract: A circuit board with anti-corrosion properties, a method for manufacturing the circuit board, and an electronic device are provided. The circuit board includes a circuit substrate, a first protective layer, and a second protective layer. The circuit substrate includes a base layer and an outer wiring layer formed on the base layer. The circuit substrate further defines a via hole connected to the outer wiring layer. The first protective layer is formed on the outer wiring layer and an inner sidewall of the via hole, and is made of a white oil. The second protective layer is formed on the first protective layer.

Abstract: The invention provides a layout pattern of static random access memory (SRAM), which at least comprises a plurality of gate structures located on a substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein the plurality of transistors comprise two pull-up transistors (PU), two pull-down transistors (PD) to form a latch circuit, and two access transistors (PG) connected to the latch circuit. In each SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein a width of the PD fin structure is wider than a width of the PG fin structure.

Abstract: A battery cell including a membrane electrode assembly, a cathode bipolar plate and an anode bipolar plate. The anode bipolar plate includes a metal layer and a thermally conductive layer. The metal layer is stacked on a side of the membrane electrode assembly that is located farthest away from the cathode bipolar plate. The metal layer has a bottom surface, a top surface, a first side surface and a second side surface. The bottom surface faces the membrane electrode assembly. The thermally conductive layer includes a first cover layer and two second cover layers. The first cover layer covers the top surface of the metal layer. The two second cover layers protrude from two opposite sides of the first cover layer, respectively. The two second cover layers at least partially cover the first side surface and the second side surface of the metal layer, respectively.

Abstract: A close-end fuel cell and an anode bipolar plate thereof are provided. The anode bipolar plate includes an airtight conductive frame and a conductive porous substrate disposed within the airtight conductive frame. In the airtight conductive frame, an edge of a first side has a fuel inlet, and an edge of a second side has a fuel outlet. The conductive porous substrate has at least one flow channel, where a first end of the flow channel communicates with the fuel inlet, a second end of the flow channel communicates with the fuel outlet. The flow channel is provided with a blocking part near the fuel inlet to divide the flow channel into two areas.

Abstract: An construction method of an embryonic chromosome signal library is provided. The construction method comprises obtaining an embryo and performing whole-genome amplification and next-generation sequencing to obtain a first chromosome signal; mapping the first chromosome signal to a chromosome reference signal to obtain a second chromosome signal; dividing the second chromosome signal within a predetermined interval range to obtain a third chromosome signal; and performing a regression correction on the sequencing read count (RC) of the third chromosome signal to obtain an embryonic chromosome signal library. Furthermore, a detection method and system of embryonic chromosomes are also provided. Thereby, the information comparison of the embryo chromosome signal library is used to determine whether the pre-implantation embryo is abnormal or not to achieve pre-implantation chromosome screening of pre-implantation embryos.

Abstract: Provided is a peptide and method in preventing or treating infections caused by a wide spectrum of pathogens, including bacteria and fungus in hosts such as plants and animals. Methods of preventing or treating plant diseases and infection in animals are also provided.

Abstract: A semiconductor substrate with an original semiconductor surface (OSS); a first gate region; a first concave formed in the semiconductor substrate and below the original semiconductor surface; a curved or depressed shape opening formed along the vertical direction of a sidewall of the semiconductor substrate in the first concave; and a first conductive region formed in the first concave and including a first doping region and a second doping region. Wherein the first doping region is formed based on the curved or depressed shape opening along the vertical direction of the sidewall of the semiconductor substrate.

Abstract: A transistor structure and a formation method thereof are provided. The transistor structure includes a transistor device, formed on an active region of a semiconductor substrate, and including: a gate structure, disposed on the active region; gate spacers, formed along opposite sidewalls of the gate structure; source/drain structures, formed in recesses of the active region at opposite sides of the gate structure; and buried isolation structures, separately extending along bottom sides of the source/drain structures. Further, a channel portion of the active region between the source/drain structures is strained as a result of a strained etching stop layer lying above or dislocation stressors formed in the source/drain structures.

Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes an access transistor defined within an active region of a semiconductor substrate and a storage capacitor disposed on the access transistor. A recessed gate structure of the access transistor extends into the active region from above the active region. Source/drain contacts of the access transistor are disposed on the active region at opposite sides of the recessed gate structure. The storage capacitor includes: a composite bottom electrode, formed by alternately stacked first conductive layers and second conductive layers, wherein each second conductive layer is sandwiched between a pair of the first conductive layers, and tunnels laterally extend through the second conductive layers, respectively; a capacitor dielectric layer, covering inner and outer surfaces of the composite bottom electrode; and a top electrode, in contact with the composite bottom electrode through the capacitor dielectric layer.

Abstract: A circuit board with anti-corrosion properties, a method for manufacturing the circuit board, and an electronic device are provided. The circuit board includes a circuit substrate, a first protective layer, and a second protective layer. The circuit substrate includes a base layer and an outer wiring layer formed on the base layer. The circuit substrate further defines a via hole connected to the outer wiring layer. The first protective layer is formed on the outer wiring layer and an inner sidewall of the via hole, and is made of a white oil. The second protective layer is formed on the first protective layer.

Abstract: A layout of a semiconductor memory device includes a substrate and a ternary content addressable memory (TCAM). The TCAM is disposed on the substrate and includes a plurality of TCAM bit cells, where at least two of the TCAM bit cells are mirror-symmetrical along an axis of symmetry, and each of the TCAM bit cells includes two storage units electrically connected to two word lines respectively, and a logic circuit electrically connected to the storage units. The logic circuit includes two first reading transistors, and two second reading transistors, where each of the second reading transistors includes a gate and source and drain regions, the source and drain regions of the second reading transistors are electrically connected to two matching lines and the first reading transistors, respectively, where the word lines are disposed parallel to and between the matching lines.

Abstract: A user requests explanation of a term. In response, a definition is provided. The user can indicate that the user does not understand a new term included in the definition. In response, explanation information is customized based on analysis of the initial term and the new term, and then the explanation information is provided to the user.

Abstract: A transistor structure includes a semiconductor substrate, a gate region, a first trench, a first isolation region and a first conductive region. The semiconductor substrate is with an original semiconductor surface. The gate region is over the semiconductor surface. The first trench is formed below the original semiconductor surface. The first isolation region is in the first trench. The first conductive region is formed with a first doping region and a second doping region; wherein the first doping region is within the semiconductor substrate and the second doping region is formed outside from the semiconductor substrate.

Abstract: A multi-laser arrangement, in particular an RGB laser module, having a housing with a housing cap having at least one opening formed therein and a transparent element associated therewith for the passing of electromagnetic radiation. The housing cap coupled to a base plate. A first laser emitting in the red spectral range, a second laser emitting in the green spectral range, and a third laser emitting in the blue spectral range are arranged in the housing. An electrical connection line is routed through the housing to each respective laser. During operation of a laser, a majority of its emitted light passes through the transparent element. Each laser is arranged on a pedestal; spaced apart from the lower surface of the base plate; and is aligned with one another. The main direction of laser emission is substantially parallel to the base plate of the housing.

Abstract: Disclosed herein are de-bondable polyurethane adhesives based on thermally expandable microspheres, obtainable or obtained by the reaction of the components of (A) at least one di- or polyisocyanate, (B) at least one polyol, (C) catalyst, (D) thermally expandable microspheres, and (E) other additives, wherein the isocyanate index of the reaction is set in the range of from 28 to 65. Additionally disclosed herein is a method of using the de-bondable polyurethane adhesives for de-bonding metal and cutting pad during wafer cutting. Further disclosed herein is a method of using the de-bondable polyurethane adhesives in mechanical property testing sample preparation.

Abstract: The invention provides a static random access memory (SRAM) array pattern, which comprises a substrate, a first region, a second region, a third region and a fourth region are defined on the substrate and arranged in an array, each region partially overlaps with the other three regions, and each region contains a SRAM cell, the layout of the SRAM cell in the first region is the same as that in the third region, the layout of the SRAM cell in the second region is the same as that in the fourth region, and the layout of the SRAM cell in the first region and the layout of the SRAM cell in the fourth region are mirror patterns along a horizontal axis.

Abstract: The present invention discloses a planar CMOSFET structure used in the peripheral circuit of DRAM chip and in sense amplifiers of array core circuit of DRAM chip, the planar CMOSFET structure comprises a planar P type MOSFET with a first conductive region, a planar N type MOSFET with a second conductive region, and a cross-shape localized isolation region between the planar P type MOSFET and the planar N type MOSFET; wherein the cross-shape localized isolation region includes a horizontally extended isolation region contacts to a bottom side of the first conductive region and a bottom side of the second conductive region.

Abstract: An air leak detection device, air leak detection method and system thereof are provided. The air leak detection method is used for a cavity. The air leak detection method includes the following steps. A scanning signal is input into the cavity. A response signal of the cavity related to the scanning signal is recorded. The response signal is analyzed to determine whether the cavity is air leaking.

Abstract: A standard cell includes plural of transistors including a first type transistor and a second type transistor, plural of contacts coupled to the transistors; at least one input line electrically coupled to the transistors; an output line electrically coupled to the transistors; a VDD contacting line electrically coupled to the transistors; a VSS contacting line electrically coupled to the transistors; wherein the first type transistor includes a first set of fin structures electrically coupled together, the second type transistor includes a second set of fin structures electrically coupled together, and a gap between the first type transistor and the second type transistor is not greater than 3×Fp minus A, wherein Fp is a pitch distance between two adjacent fin structures in the first type transistor and A is a minimum feature size of the standard cell.