Abstract: A wearable sweat sensor for detecting one or more analytes in human sweat comprises an optical module comprising at least one light source and at least one light detector; at least one sensor layer optically coupled to the optical module and having optical absorbance properties that are dependent on the concentration of a target analyte of said one or more analytes; and one or more processors in communication with the optical module. The one or more processors are configured to: cause light from the at least one light source to be transmitted towards, and/or through, the at least one sensor layer; obtain, from the at least one light detector, one or more optical signals reflected and/or transmitted from the at least one sensor layer; and determine, from at least one wavelength component of the one or more optical signals, a target analyte concentration.

Abstract: A high voltage logic circuit for high voltage system application comprises a first device layer formed from a first semiconductor material and comprises a low voltage logic circuit; and a second device layer formed from a second different semiconductor material and comprising one or more components of an additional circuit for generating a high voltage logic output from a low voltage logic input from the low voltage logic circuit; wherein the first and second device layers are integrally formed.

Abstract: A high voltage logic circuit for high voltage system application comprises a first device layer formed from a first semiconductor material and comprises a low voltage logic circuit; and a second device layer formed from a second different semiconductor material and comprising one or more components of an additional circuit for generating a high voltage logic output from a low voltage logic input from the low voltage logic circuit; wherein the first and second device layers are integrally formed.

Abstract: A high voltage logic circuit for high voltage system application comprises a first device layer formed from a first semiconductor material and comprises a low voltage logic circuit; and a second device layer formed from a second different semiconductor material and comprising one or more components of an additional circuit for generating a high voltage logic output from a low voltage logic input from the low voltage logic circuit; wherein the first and second device layers are integrally formed.

Abstract: A high voltage logic circuit for high voltage system application comprises a first device layer formed from a first semiconductor material and comprises a low voltage logic circuit; and a second device layer formed from a second different semiconductor material and comprising one or more components of an additional circuit for generating a high voltage logic output from a low voltage logic input from the low voltage logic circuit; wherein the first and second device layers are integrally formed.

Abstract: A method of forming an integrated circuit is disclosed. The method includes: (i) forming at least a pair of optoelectronic devices from at least a first wafer material arranged on a semiconductor substrate, the first wafer material different to silicon; (ii) etching the first wafer material to form a first recess to be filled with a second material; (iii) processing the second material to form a waveguide for coupling the pair of optoelectronic devices to define an optical interconnect; and (iv) bonding at least one partially processed CMOS device layer having at least one transistor to the second semiconductor substrate to form the integrated circuit, the partially processed CMOS device layer arranged adjacent to the optical interconnect. An integrated circuit is also disclosed.

Abstract: A method of forming an integrated circuit is disclosed. The method includes: (i) forming at least a pair of optoelectronic devices from at least a first wafer material arranged on a semiconductor substrate, the first wafer material different to silicon; (ii) etching the first wafer material to form a first recess to be filled with a second material; (iii) processing the second material to form a waveguide for coupling the pair of optoelectronic devices to define an optical interconnect; and (iv) bonding at least one partially processed CMOS device layer having at least one transistor to the second semiconductor substrate to form the integrated circuit, the partially processed CMOS device layer arranged adjacent to the optical interconnect. An integrated circuit is also disclosed.

Abstract: A method (100) of forming an integrated circuit is disclosed. The method comprises: (i) forming at least a pair of optoelectronic devices from at least a first wafer material arranged on a semiconductor substrate, the first wafer material different to silicon; (ii) etching the first wafer material to form a first recess to be filled with a second material; (iii) processing (104) the second material to form a waveguide for coupling the pair of optoelectronic devices to define an optical interconnect; and (iv) bonding (106) at least one partially processed CMOS device layer having at least one transistor to the second semiconductor substrate to form the integrated circuit, the partially processed CMOS device layer arranged adjacent to the optical interconnect. An integrated circuit is also disclosed.

Abstract: An integrated circuit (400) adapted for mobile communication is disclosed. The circuit comprises a first device layer formed of a first semiconductor material and having at least a first circuit portion (402); and a second device layer formed of a second semiconductor material different to the first semiconductor material and having at least a second circuit portion (404), wherein the first and second device layers are integrally formed, and the first circuit portion is electrically coupled to the second circuit portion to enable the mobile communication using first and second wireless communication protocols. A related mobile computing device is also disclosed.

Abstract: A method (100) of forming an integrated circuit is disclosed. The method comprises: (i) forming at least a pair of optoelectronic devices from at least a first wafer material arranged on a semiconductor substrate, the first wafer material different to silicon; (ii) etching the first wafer material to form a first recess to be filled with a second material; (iii) processing (104) the second material to form a waveguide for coupling the pair of optoelectronic devices to define an optical interconnect; and (iv) bonding (106) at least one partially processed CMOS device layer having at least one transistor to the second semiconductor substrate to form the integrated circuit, the partially processed CMOS device layer arranged adjacent to the optical interconnect. An integrated circuit is also disclosed.

Abstract: An integrated circuit (400) adapted for mobile communication is disclosed. The circuit comprises a first device layer formed of a first semiconductor material and having at least a first circuit portion (402); and a second device layer formed of a second semiconductor material different to the first semiconductor material and having at least a second circuit portion (404), wherein the first and second device layers are integrally formed, and the first circuit portion is electrically coupled to the second circuit portion to enable the mobile communication using first and second wireless communication protocols. A related mobile computing device is also disclosed.

Abstract: A technique for generating interconnect fabric requirements. The technique programmatically generates an interconnect design problem based on criteria specified by a user. In one aspect, a computer implemented method is provided for generating an interconnect fabric design problem. The problem includes requirements for a plurality of flows among a set of network nodes. A source node and a terminal node are selected, from among the set of network nodes, for a flow to be added to the requirements. A maximum capacity available at the selected source node and the selected terminal node is determined. The flow is generated having a capacity less than or equal to the lower of the maximum capacity of the source node and the terminal node. Depending upon the input criteria, the invention may generate problems with greater flexibility than prior techniques.

Abstract: A technique for generating interconnect fabric requirements. The technique programmatically generates an interconnect design problem based on criteria specified by a user. In one aspect, a computer implemented method is provided for generating an interconnect fabric design problem. The problem includes requirements for a plurality of flows among a set of network nodes. A source node and a terminal node are selected, from among the set of network nodes, for a flow to be added to the requirements. A maximum capacity available at the selected source node and the selected terminal node is determined. The flow is generated having a capacity less than or equal to the lower of the maximum capacity of the source node and the terminal node. Depending upon the input criteria, the invention may generate problems with greater flexibility than prior techniques.