Abstract: The disclosure relates to a mount assembly for add-in card including a base plate, a tray, and a handle. The tray is slidably disposed on the base plate. The handle includes a pivot portion and a tray installation portion. The pivot portion is pivotally disposed on the base plate. The tray installation portion is pivotally and slidably disposed on the tray. In addition, the disclosure also relates to an electronic device having the mount assembly and a chassis for the electronic device.

Abstract: A handle device is configured for a chassis body. The chassis body includes a main part and a cover plate. The handle device includes a base part and a handle part. The base part is disposed on the cover plate. The handle part includes an operative part, a coupling part and a shaft part. The coupling part is connected to the operative part. The shaft part is connected to the coupling part. The coupling part of the handle part is pivotally coupled to the base part. The shaft part is rotatably disposed on the main part. The handle part is movable relative to the base part so as to disengage the cover plate from the main part.

Abstract: A handle device is configured for a chassis body. The chassis body includes a main part and a cover plate. The handle device includes a base part and a handle part. The base part is disposed on the cover plate. The handle part includes an operative part, a coupling part and a shaft part. The coupling part is connected to the operative part. The shaft part is connected to the coupling part. The coupling part of the handle part is pivotally coupled to the base part. The shaft part is rotatably disposed on the main part. The handle part is movable relative to the base part so as to disengage the cover plate from the main part.

Abstract: The disclosure relates to a mount assembly for add-in card including a base plate, a tray, and a handle. The tray is slidably disposed on the base plate. The handle includes a pivot portion and a tray installation portion. The pivot portion is pivotally disposed on the base plate. The tray installation portion is pivotally and slidably disposed on the tray. In addition, the disclosure also relates to an electronic device having the mount assembly and a chassis for the electronic device.

Abstract: Systems and methods for maximizing the breakdown voltage of a semiconductor device are described. In a multiple floating guard ring design, the spacing between two consecutive sets of floating guard rings may increase with their distance from the main junction while maintaining depletion region overlap, thereby alleviating crowding and optimally spreading the electric field leading to a breakdown voltage that is close to the intrinsic material limit. In another exemplary embodiment, fabrication of floating guard rings simultaneously with the formation of another semiconductor feature allows precise positioning of the first floating guard ring with respect to the edge of a main junction, as well as precise control of floating guard ring widths and spacings. In yet another exemplary embodiment, design of the vertical separation between doped regions of a semiconductor device adjusts the device's gate-to-source breakdown voltage without affecting the device's pinch-off voltage.

Abstract: Systems and methods for maximizing the breakdown voltage of a semiconductor device are described. In a multiple floating guard ring design, the spacing between two consecutive sets of floating guard rings may increase with their distance from the main junction while maintaining depletion region overlap, thereby alleviating crowding and optimally spreading the electric field leading to a breakdown voltage that is close to the intrinsic material limit. In another exemplary embodiment, fabrication of floating guard rings simultaneously with the formation of another semiconductor feature allows precise positioning of the first floating guard ring with respect to the edge of a main junction, as well as precise control of floating guard ring widths and spacings. In yet another exemplary embodiment, design of the vertical separation between doped regions of a semiconductor device adjusts the device's gate-to-source breakdown voltage without affecting the device's pinch-off voltage.

Abstract: A method of making a semiconductor structure for use in a static induction transistor. Three layers of a SiC material are on a substrate with the top layer covered with a thick oxide. A mask having a plurality of strips is deposited on the top of the oxide to protect the area underneath it, and an etch removes the oxide, the third layer and a small amount of the second layer, leaving a plurality of pillars. An oxidation step grows an oxide skirt around the base of each pillar and consumes the edge portions of the third layer under the oxide to form a source. An ion implantation forms gate regions between the skirts. At the same time, a plurality of guard rings is formed. Removal of all oxide results in a semiconductor structure to which source, gate and drain connections may be made to form a static induction transistor. A greater separation between a source and gate is obtained by placing a spacer layer on the sidewalls of the pillars, either before or after formation of the skirt.

Abstract: In one embodiment, the disclosure relates to a method for forming a semiconductor power device by depositing a first layer of TiW on a gate region and a source region, depositing a second layer of refractory metal over the first layer of TiW at the gate region, depositing a dielectric stack over the second layer of refractory metal and a portion of the first layer of TiW, depositing an etch stop layer over a portion of the dielectric stack, depositing an interconnect layer over the etch stop layer and the dielectric stack and depositing an etch mask over the interconnect layer.

Abstract: A structure for use in a static induction transistor includes a semiconductor body having first and second semiconductor layers on a substrate, with the second layer having a dopant concentration of around an order of magnitude higher than the dopant concentration of the first layer. A plurality of sources are located on the second layer. A plurality of gates are ion implanted in the second layer, an end one of the gates being connected to all of the plurality of gates and constituting a gate bus. The gate bus has an extension connecting the gate bus in the second layer of higher dopant concentration to the first layer of lower dopant concentration. The extension is ion implanted in either a series of steps or a sloping surface which is formed in the first and second layers.

Abstract: A structure for use in a static induction transistor includes a semiconductor body having first and second semiconductor layers on a substrate, with the second layer having a dopant concentration of around an order of magnitude higher than the dopant concentration of the first layer. A plurality of sources are located on the second layer. A plurality of gates are ion implanted in the second layer, an end one of the gates being connected to all of the plurality of gates and constituting a gate bus. The gate bus has an extension connecting the gate bus in the second layer of higher dopant concentration to the first layer of lower dopant concentration. The extension is ion implanted in either a series of steps or a sloping surface which is formed in the first and second layers.

Abstract: A method of making a semiconductor structure for use in a static induction transistor. Three layers of a SiC material are on a substrate with the top layer covered with a thick oxide. A mask having a plurality of strips is deposited on the top of the oxide to protect the area underneath it, and an etch removes the oxide, the third layer and a small amount of the second layer, leaving a plurality of pillars. An oxidation step grows an oxide skirt around the base of each pillar and consumes the edge portions of the third layer under the oxide to form a source. An ion implantation forms gate regions between the skirts. At the same time, a plurality of guard rings is formed. Removal of all oxide results in a semiconductor structure to which source, gate and drain connections may be made to form a static induction transistor.

Abstract: A plurality of electronic circuits and associated signal lines are positioned at respective locations on a base wafer. A cover wafer, which fits over the base wafer, includes a corresponding like number of locations each including one or more cavities to accommodate the electronic circuit and associated signal lines. The cover wafer includes a plurality of vias for making electrical connection to the signal lines. A multi layer metallic arrangement hermetically seals the periphery of each location as well as sealing the bottom of each via. The joined base and cover wafers may then be diced to form individual die packages.

Abstract: A plurality of electronic circuits and associated signal lines are positioned at respective locations on a base wafer. A cover wafer, which fits over the base wafer, includes a corresponding like number of locations each including one or more cavities to accommodate the electronic circuit and associated signal lines. The cover wafer includes a plurality of vias for making electrical connection to the signal lines. A multi layer metallic arrangement hermetically seals the periphery of each location as well as sealing the bottom of each via. The joined base and cover wafers may then be diced to form individual die packages.

Abstract: A plurality of electronic circuits and associated signal lines are positioned at respective locations on a base wafer. A cover wafer, which fits over the base wafer, includes a corresponding like number of locations each including one or more cavities to accommodate the electronic circuit and associated signal lines. The cover wafer includes a plurality of vias for making electrical connection to the signal lines. A multi layer metallic arrangement hermetically seals the periphery of each location as well as sealing the bottom of each via. The joined base and cover wafers may then be diced to form individual die packages.

Abstract: A plurality of electronic circuits and associated signal lines are positioned at respective locations on a base wafer. A cover wafer, which fits over the base wafer, includes a corresponding like number of locations each including one or more cavities to accommodate the electronic circuit and associated signal lines. The cover wafer includes a plurality of vias for making electrical connection to the signal lines. A multi layer metallic arrangement hermetically seals the periphery of each location as well as sealing the bottom of each via. The joined base and cover wafers may then be diced to form individual die packages.

Abstract: A capacitive type MEMS switch having a conductor arrangement comprised of first and second RF conductors deposited on a substrate. A bridge member having a central enlarged portion is positioned over the conductor arrangement. In one embodiment, the first RF conductor has an end defining an open area in which is positioned a pull down electrode, with the end of the first RF conductor substantially surrounding the pull down electrode. In another embodiment, two opposed RF conductors, each having ends with first and second branches, define an open area in which a pull down electrode is positioned. A dielectric layer is deposited on the conductor arrangement such that when a pull down voltage is applied to the pull down electrode, the switch impedance is significantly reduced so as to allow signal propagation between the RF conductors.

Abstract: A capacitive type MEMS switch having a conductor arrangement comprised of first and second RF conductors deposited on a substrate. A bridge member having a central enlarged portion is positioned over the conductor arrangement. In one embodiment, the first RF conductor has an end defining an open area in which is positioned a pull down electrode, with the end of the first RF conductor substantially surrounding the pull down electrode. In another embodiment, two opposed RF conductors, each having ends with first and second branches, define an open area in which a pull down electrode is positioned. A dielectric layer is deposited on the conductor arrangement such that when a pull down voltage is applied to the pull down electrode, the switch impedance is significantly reduced so as to allow signal propagation between the RF conductors.

Abstract: A die attach procedure for SiC uses the scrubbing technique to bond a SiC die to a package. A first layer is formed on the SiC die. This first layer, preferably of nickel, bonds to the SiC die. A second layer, preferably amorphous silicon, is then formed on the first layer. The second layer bonds to the first layer, and forms a eutectic with the material, usually gold, plating the package when the SiC die is scrubbed onto the package.

Abstract: A method of aligning a gate and a source of a silicon carbide static induction transistor comprising the steps of depositing an oxide layer over the transistor, forming oxide spacers from the oxide layer where the oxide spacers are adjacent the source, depositing a metal layer over the transistor and removing the oxide spacers so that the resulting gates are accurately aligned with the source.