Patents by Inventor Li Shu

Li Shu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7171493
    Abstract: An apparatus for transmitting a file with enhanced transmission security through a network includes a file-splitting processor that splits the file into a plurality of message segments and addresses the plurality of message segments to a plurality of addresses assigned to a receiving host. The apparatus includes a message segment transmitter for transmitting the plurality of message segments to the receiving host.
    Type: Grant
    Filed: December 19, 2001
    Date of Patent: January 30, 2007
    Assignee: The Charles Stark Draper Laboratory
    Inventors: Li Shu, William Weinstein
  • Publication number: 20070009732
    Abstract: A method for labeling fabrics, such as fabric garments, and a heat-transfer label (311) well-suited for use in said method. In one embodiment, the heat-transfer label (311) comprises (i) a support portion (313), the support portion (313) comprising a carrier (315) and a release layer (317); (ii) a wax layer (319), the wax layer overcoating the release layer (317); and (iii) a transfer portion (321), the transfer portion (321) comprising an adhesive layer (323) printed directly onto the wax layer (319) and an ink design layer (325) printed directly onto the adhesive layer (323). Each of the adhesive layer (323) and the ink design layer includes a non-cross-linked PVC resin. The ink design layer may be screen printed onto the adhesive layer (323) or may be printed onto the adhesive layer (323) using thermal transfer printing, ink jet printing or laser printing.
    Type: Application
    Filed: December 2, 2003
    Publication date: January 11, 2007
    Inventors: Kuolih Tsai, Dong-Tsai Hseih, Li Shu, David Edwards, Alan Morgenthau, Yi-Hung Chiao, Xiao-Ming He, Yukihiko Sasaki, Scott Ferguson
  • Patent number: 7034819
    Abstract: An apparatus for generating an interleaved stereo image includes a 3D graphics engine, an interleaved data merger and a register. The 3D graphics engine generates a shrunken left-eye image and a shrunken right-eye image of a stereo image based on video source data, the vertical sizes of the shrunken left-eye image and the shrunken right-eye image are shrunk compared with the vertical size of the video source data. The interleaved data merger stores the shrunken left-eye image and the shrunken right-eye image into two consecutive memory segments, and scans the memory segments while displaying the stereo image. A register controls a line number of a display region, so that the rows of the left-eye image shrunk and the right-eye image shrunk arrive at the display region in line-interleaved order. The invention also discloses a method for generating an interleaved stereo image.
    Type: Grant
    Filed: October 4, 2002
    Date of Patent: April 25, 2006
    Assignee: Silicon Integrated Systems Corp.
    Inventors: Ruen-rone Lee, Li-shu Lu, Shih-chin Lin
  • Patent number: 7027664
    Abstract: A method for removing noise regions in a stereo 3D image, which includes a first eye image and a second eye image is achieved by calculating a maximum offset value and turning a horizontal synchronization signal and a display enable signal of the CRT timing parameters.
    Type: Grant
    Filed: March 11, 2002
    Date of Patent: April 11, 2006
    Assignee: Silicon Integrated Systems Corporation
    Inventors: Ruen-Rone Lee, Li-Shu Lu, Yu-Ming Huang
  • Patent number: 6939784
    Abstract: A plurality of electronic circuits and associated signal lines are positioned at respective locations on a base wafer. A cover wafer, which fits over the base wafer, includes a corresponding like number of locations each including one or more cavities to accommodate the electronic circuit and associated signal lines. The cover wafer includes a plurality of vias for making electrical connection to the signal lines. A multi layer metallic arrangement hermetically seals the periphery of each location as well as sealing the bottom of each via. The joined base and cover wafers may then be diced to form individual die packages.
    Type: Grant
    Filed: April 9, 2004
    Date of Patent: September 6, 2005
    Assignee: Northrop Grumman Corporation
    Inventors: Li-Shu Chen, Philip C. Smith, Thomas J. Moloney, Howard Fudem
  • Publication number: 20050190717
    Abstract: An apparatus and method for transmitting a file via a communications network predicts a location where a destination node will be at upon arrival of a message unit relayed via the network. An intermediate node is selected for relaying the message unit between a source node and the destination node in response to the predicted location of the destination node. The apparatus may include a location prediction processor and a relay node selector.
    Type: Application
    Filed: March 1, 2004
    Publication date: September 1, 2005
    Applicant: The Charles Stark Draper Laboratory
    Inventors: Li Shu, John Turkovich
  • Publication number: 20050153113
    Abstract: A label assembly and method of using the same to label articles durably, yet removably. In one embodiment, the label assembly is used to label fabric articles, such as clothing, and comprises (a) an image forming laminate for forming an image on the fabric article, the image forming laminate comprising an ink layer, the ink layer being bondable to the fabric article; and (b) an image removing laminate for removing the image from the fabric article, the image removing laminate comprising a remover layer, the remover layer, upon being activated by heat and/or light, being bondable to the ink layer of the image forming laminate; (c) whereby, upon bonding of the image removing laminate to the ink layer, the bonding between the image removing laminate and the ink layer is stronger than the bonding between the ink layer and the fabric article.
    Type: Application
    Filed: January 9, 2004
    Publication date: July 14, 2005
    Inventors: Dong-Tsai Hseih, Kuolih Tsai, Yi-Hung Chiao, Xiao-Ming He, Li Shu, Ramin Heydarpour, Alan Morgenthau
  • Publication number: 20050110454
    Abstract: A solar electricity generating system includes a solar cell and a DC/AC converter coupled to the cell. The first proposed method includes the steps of: (a) adjusting an output current of the DC/AC converter; (b) sensing an output voltage variation of the solar cell; (c) adjusting the output current in a direction of the variation; and (d) repeating the steps (a) to (c). The second proposed method includes the steps of: (a) adjusting a DC output voltage of the solar cell; (b) sensing an output current amplitude variation of the DC/AC converter; (c) adjusting the output voltage in a direction of the variation; and (d) repeating the steps (a) to (c).
    Type: Application
    Filed: November 19, 2004
    Publication date: May 26, 2005
    Inventors: Wen-Yin Tsai, Hung-Liang Chou, Chin-Chang Wu, Kuen-Der Wu, Chun-Li Shu
  • Publication number: 20050100689
    Abstract: A method for labeling fabrics, such as fabric garments, and a heat-transfer label well-suited for use in said method. In one embodiment, the heat-transfer label comprises (i) a support portion, the support portion comprising a carrier and a release layer; (ii) a wax layer, the wax layer overcoating the release layer; and (iii) a transfer portion, the transfer portion comprising an adhesive layer printed onto the wax layer and an ink design layer printed onto the adhesive layer. Preferably, at least a portion of the ink design layer is printed using a variable printing technique, such as thermal transfer printing.
    Type: Application
    Filed: July 30, 2004
    Publication date: May 12, 2005
    Inventors: Xiao-Ming He, Liviu Dinescu, Kuolih Tsai, Dong-Tsai Hseih, Li Shu, Yi-Hung Chiao, Alan Morgenthau, Ramin Heydarpour
  • Patent number: 6812558
    Abstract: A plurality of electronic circuits and associated signal lines are positioned at respective locations on a base wafer. A cover wafer, which fits over the base wafer, includes a corresponding like number of locations each including one or more cavities to accommodate the electronic circuit and associated signal lines. The cover wafer includes a plurality of vias for making electrical connection to the signal lines. A multi layer metallic arrangement hermetically seals the periphery of each location as well as sealing the bottom of each via. The joined base and cover wafers may then be diced to form individual die packages.
    Type: Grant
    Filed: March 26, 2003
    Date of Patent: November 2, 2004
    Assignee: Northrop Grumman Corporation
    Inventors: Li-Shu Chen, Philip C. Smith, Thomas J. Moloney, Howard Fudem
  • Publication number: 20040188821
    Abstract: A plurality of electronic circuits and associated signal lines are positioned at respective locations on a base wafer. A cover wafer, which fits over the base wafer, includes a corresponding like number of locations each including one or more cavities to accommodate the electronic circuit and associated signal lines. The cover wafer includes a plurality of vias for making electrical connection to the signal lines. A multi layer metallic arrangement hermetically seals the periphery of each location as well as sealing the bottom of each via. The joined base and cover wafers may then be diced to form individual die packages.
    Type: Application
    Filed: March 26, 2003
    Publication date: September 30, 2004
    Inventors: Li-Shu Chen, Philip C. Smith, Thomas J. Moloney, Howard Fudem
  • Publication number: 20040191957
    Abstract: A plurality of electronic circuits and associated signal lines are positioned at respective locations on a base wafer. A cover wafer, which fits over the base wafer, includes a corresponding like number of locations each including one or more cavities to accommodate the electronic circuit and associated signal lines. The cover wafer includes a plurality of vias for making electrical connection to the signal lines. A multi layer metallic arrangement hermetically seals the periphery of each location as well as sealing the bottom of each via. The joined base and cover wafers may then be diced to form individual die packages.
    Type: Application
    Filed: April 9, 2004
    Publication date: September 30, 2004
    Applicant: NORTHROP GRUMMAN CORPORATION
    Inventors: Li-Shu Chen, Philip C. Smith, Thomas J. Moloney, Howard Fudem
  • Patent number: 6777765
    Abstract: A capacitive type MEMS switch having a conductor arrangement comprised of first and second RF conductors deposited on a substrate. A bridge member having a central enlarged portion is positioned over the conductor arrangement. In one embodiment, the first RF conductor has an end defining an open area in which is positioned a pull down electrode, with the end of the first RF conductor substantially surrounding the pull down electrode. In another embodiment, two opposed RF conductors, each having ends with first and second branches, define an open area in which a pull down electrode is positioned. A dielectric layer is deposited on the conductor arrangement such that when a pull down voltage is applied to the pull down electrode, the switch impedance is significantly reduced so as to allow signal propagation between the RF conductors.
    Type: Grant
    Filed: December 19, 2002
    Date of Patent: August 17, 2004
    Assignee: Northrop Grumman Corporation
    Inventors: Li-Shu Chen, Howard N. Fudem, Donald E. Crockett, Philip C. Smith
  • Publication number: 20040119126
    Abstract: A capacitive type MEMS switch having a conductor arrangement comprised of first and second RF conductors deposited on a substrate. A bridge member having a central enlarged portion is positioned over the conductor arrangement. In one embodiment, the first RF conductor has an end defining an open area in which is positioned a pull down electrode, with the end of the first RF conductor substantially surrounding the pull down electrode. In another embodiment, two opposed RF conductors, each having ends with first and second branches, define an open area in which a pull down electrode is positioned. A dielectric layer is deposited on the conductor arrangement such that when a pull down voltage is applied to the pull down electrode, the switch impedance is significantly reduced so as to allow signal propagation between the RF conductors.
    Type: Application
    Filed: December 19, 2002
    Publication date: June 24, 2004
    Inventors: Li-Shu Chen, Howard N. Fudem, Donald E. Crockett, Philip C. Smith
  • Publication number: 20040066450
    Abstract: An apparatus for generating an interleaved stereo image includes a 3D graphics engine, an interleaved data merger and a register. The 3D graphics engine generates a shrunken left-eye image and a shrunken right-eye image of a stereo image based on video source data, the vertical sizes of the shrunken left-eye image and the shrunken right-eye image are shrunk compared with the vertical size of the video source data. The interleaved data merger stores the shrunken left-eye image and the shrunken right-eye image into two consecutive memory segments, and scans the memory segments while displaying the stereo image. A register controls a line number of a display region, so that the rows of the left-eye image shrunk and the right-eye image shrunk arrive at the display region in line-interleaved order. The invention also discloses a method for generating an interleaved stereo image.
    Type: Application
    Filed: October 4, 2002
    Publication date: April 8, 2004
    Inventors: Ruen-Rone Lee, Li-Shu Lu, Shih-Chin Lin
  • Publication number: 20030115364
    Abstract: An apparatus for transmitting a file through a network includes a file-splitting processor that splits the file into a plurality of message segments and addresses the plurality of message segments to a plurality of addresses assigned to a receiving host. The apparatus includes a message segment transmitter for transmitting the plurality of message segments to the receiving host.
    Type: Application
    Filed: December 19, 2001
    Publication date: June 19, 2003
    Inventors: Li Shu, William Weinstein
  • Patent number: 6577307
    Abstract: An anti-aliasing process without sorting the polygons in depth order to improve the image quality in three-dimensional graphics system. This method comprises extra buffer memory than does a typical three-dimensional graphics display system. The Z buffer stores the depth value of nearest pixel in front Z buffer and depth value of secondary nearest pixels in back Z buffer. The color buffer stores foreground color and background color. A weighting value is used and stored in the frame buffer to blend the foreground color and the background nearest color. The weighting value is associated with each pixel, it indicates the percentage of coverage of a pixel. Every pixel in Z buffer test stage will update the depth of the nearest pixel and the depth of the second nearest in Z-buffer, foreground color and background color in the frame buffer and the weighting value according to the result of depth comparison.
    Type: Grant
    Filed: September 20, 1999
    Date of Patent: June 10, 2003
    Assignee: Silicon Integrated Systems Corp.
    Inventors: Chien-Chung Hsiao, Li-Shu Lu
  • Publication number: 20030103062
    Abstract: An apparatus for controlling a display, which includes an on-screen buffer, two overlay buffers and a stereo window controller. The on-screen buffer stores screen image data that includes image data of an overlay region. The two overlay buffers are of a double-buffered architecture, and one overlay buffer stores the left image data and the right image data of a current frame, and another overlay buffer stores the left image data and the right image data of a next frame. The stereo window controller controls swap operations and overlay operations, wherein the swap operations determine which one of the two overlay buffers stores the left image data and the right image data of the current frame, and the overlay operations alternatively output the left image data and the right image data of the current frame while the overlay region is being scanned.
    Type: Application
    Filed: November 30, 2001
    Publication date: June 5, 2003
    Inventors: Ruen-Rone Lee, Li-Shu Lu, Shih-Chin Lin
  • Publication number: 20030084020
    Abstract: The invention features an apparatus and method for facilitating reliable storage of a file. The apparatus includes a file processor that converts the file into N storage segments. The N segments enable reassembly of the file from a subset of any M of the storage segments. N and M are positive integers, and N >M≧1. The apparatus includes means facilitating storage of at least M of the N storage segments.
    Type: Application
    Filed: December 19, 2001
    Publication date: May 1, 2003
    Inventor: Li Shu
  • Publication number: 20030071892
    Abstract: A method for removing noise regions in a stereo 3D image, which includes a first eye image and a second eye image is achieved by calculating a maximum offset value and turning a horizontal synchronization signal and a display enable signal of the CRT timing parameters.
    Type: Application
    Filed: March 11, 2002
    Publication date: April 17, 2003
    Applicant: Silicon Integrated Systems Corporation
    Inventors: Ruen-Rone Lee, Li-Shu Lu, Yu-Ming Huang