Patents by Inventor Li-Te Lin
Li-Te Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220367201Abstract: A method of reducing corner rounding during patterning of a substrate to form a prescribed pattern comprising a corner includes dividing the pattern into a first pattern and a second pattern, the first pattern forming a first edge of the corner and the second pattern forming a second edge of the corner. At least a portion of the second pattern overlaps the first pattern such that the first edge intersects with the second edge to form a corner of the prescribed pattern. The method further includes forming the first pattern in a first mask layer disposed on a substrate to expose the substrate and forming the second pattern in the first mask layer to expose the substrate. The substrate exposed through the first mask layer is then etched to obtain the pattern.Type: ApplicationFiled: July 25, 2022Publication date: November 17, 2022Inventors: Chin-Yuan TSENG, Yu-Tien SHEN, Wei-Liang LIN, Chih-Ming LAI, Kuo-Cheng CHING, Shi-Ning JU, Li-Te LIN, Ru-Gun LIU
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Publication number: 20220359724Abstract: A method includes forming a semiconductor fin on a substrate; forming a dielectric layer over the semiconductor fin; forming a metal gate electrode in the dielectric layer and extending across the semiconductor fin; forming a source/drain regions on the semiconductor fin and on opposite sides of the metal gate electrode; performing a first non-zero bias plasma etching process to the metal gate electrode; after performing the first non-zero bias plasma etching process, performing a first zero bias plasma etching process to the metal gate electrode.Type: ApplicationFiled: July 26, 2022Publication date: November 10, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Chen LO, Li-Te LIN, Pinyen LIN
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Publication number: 20220344168Abstract: A patterning method includes at least the following steps. A first material layer is provided. A second material layer is provided over the first material layer. The second material layer partially exposes the first material layer. A passivation layer is formed over the first material layer and the second material layer. A growth rate of the passivation layer on the second material layer is greater than a growth rate of the passivation layer on the first material layer. A first etching process is performed to remove a portion of the passivation layer and a portion of the first material layer.Type: ApplicationFiled: April 22, 2021Publication date: October 27, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Christine Y. Ouyang, Li-Te Lin
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Publication number: 20220344486Abstract: A semiconductor device and methods of fabricating the same are disclosed. The method can include forming a fin structure on a substrate, forming a source/drain (S/D) region on the fin structure, forming a gate structure on the fin structure adjacent to the S/D region, and forming a capping structure on the gate structure. The forming the capping structure includes forming a conductive cap on the gate structure, forming a cap liner on the conductive cap, and forming a carbon-based cap on the cap liner. The method further includes forming a first contact structure on the S/D region, forming an insulating cap on the first contact structure, and forming a second contact structure on the conductive cap.Type: ApplicationFiled: April 23, 2021Publication date: October 27, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Chin CHANG, Ming-Huan Tsai, Li-Te Lin, Pinyen Lin
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Publication number: 20220336635Abstract: A method for forming a semiconductor device structure is provided. The method includes forming first semiconductor layers and second semiconductor layers on a substrate, and the first semiconductor layers and the second semiconductor layers are alternately stacked. The method includes forming a dummy gate structure over the first semiconductor layers and the second semiconductor layers, and removing a portion of the first semiconductor layers and second semiconductor layers to form a S/D trench. The method also includes removing the second semiconductor layers to form a recess connected to the S/D trench. The method includes forming a dummy dielectric layer in the recess after the dummy gate structure is formed, and the dummy dielectric layer is exposed by the S/D trench. The method includes removing a portion of the dummy dielectric layer to form a cavity and forming an inner spacer layer in the cavity.Type: ApplicationFiled: June 30, 2022Publication date: October 20, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tze-Chung LIN, Han-Yu LIN, Li-Te LIN, Pinyen LIN
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Publication number: 20220336611Abstract: The present disclosure describes a method to form a semiconductor device with air inner spacers. The method includes forming a semiconductor structure on a first side of a substrate. The semiconductor structure includes a fin structure having multiple semiconductor layers on the substrate, an epitaxial structure on the substrate and in contact with the multiple semiconductor layers, a gate structure wrapped around the multiple semiconductor layers, and an inner spacer structure between the gate structure and the epitaxial structure. The method further includes removing a portion of the substrate from a second side of the substrate to expose the epitaxial structure and the inner spacer structure, forming an oxide layer on the epitaxial structure on the second side of the substrate, and removing a portion of the inner spacer structure to form an opening. The second side is opposite to the first side of the substrate.Type: ApplicationFiled: September 10, 2021Publication date: October 20, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Fo-Ju LIN, Fang-Wei Lee, Chih-Long Chiang, Li-Te Lin, Pinyen Lin
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Publication number: 20220336623Abstract: A semiconductor device includes first and second gate structures over a substrate, the first gate structure has a first width that is smaller than a second width of the second gate structure, in which a lower portion of the first gate structure having a first work-function material (WFM) layer, the first WFM layer having a top surface, a lower portion of the second gate structure having a second WFM layer, the second WFM layer having a top surface. A first gate electrode is disposed over the first WFM layer and a second gate electrode has a lower portion disposed in the second WFM layer, in which the first gate electrode has a first width that is smaller than a second width of the second gate electrode, and wherein the top surface of the second WFM layer is at a level below a top surface of the second gate electrode.Type: ApplicationFiled: July 1, 2022Publication date: October 20, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Chen LO, Jung-Hao CHANG, Li-Te LIN, Pinyen LIN
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Patent number: 11469143Abstract: A semiconductor device includes a semiconductor substrate, a source/drain region, a source/drain contact, a conductive via and a first polymer layer. The source/drain region is in the semiconductor substrate. The source/drain contact is over the source/drain region. The source/drain via is over the source/drain contact. The first polymer layer extends along a first sidewall of the conductive via and is separated from a second sidewall of the conductive via substantially perpendicular to the first sidewall of the conductive via.Type: GrantFiled: September 25, 2020Date of Patent: October 11, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Po-Chin Chang, Li-Te Lin, Pinyen Lin
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Publication number: 20220319861Abstract: A technique for semiconductor manufacturing is provided. The technique includes the operations as follows. A semiconductor structure having a first material is received. A plurality of first main etches are performed to the semiconductor structure for a plurality of first durations under the first etching chemistry. A plurality of pumping operations are performed for a plurality of pumping durations, each of the pumping operations being prior to each of the first main etches. Each of the first durations is in a range of from about 1 second to about 2.5 seconds.Type: ApplicationFiled: June 24, 2022Publication date: October 6, 2022Inventors: HAN-YU LIN, LI-TE LIN, TZE-CHUNG LIN, FANG-WEI LEE, YI-LUN CHEN, JUNG-HAO CHANG, YI-CHEN LO, FO-JU LIN, KENICHI SANO, PINYEN LIN
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Publication number: 20220297234Abstract: A semiconductor fabrication apparatus includes a source chamber being operable to generate charged particles; and a processing chamber integrated with the source chamber and configured to receive the charged particles from the source chamber. The processing chamber includes a wafer stage being operable to secure and move a wafer, and a laser-charged particles interaction module that further includes a laser source to generate a first laser beam; a beam splitter configured to split the first laser beam into a second laser beam and a third laser beam; and a mirror configured to reflect the third laser beam such that the third laser beam is redirected to intersect with the second laser beam to form a laser interference pattern at a path of the charged particles, and wherein the laser interference pattern modulates the charged particles by in a micron-zone mode for processing the wafer using the modulated charged particles.Type: ApplicationFiled: June 6, 2022Publication date: September 22, 2022Inventors: Chansyun David Yang, Li-Te Lin, Pinyen Lin
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Patent number: 11424341Abstract: A semiconductor device includes a substrate, a semiconductor fin, a gate electrode, a pair of gate spacers, a dielectric cap, and a hard mask layer. The semiconductor fin extends upwardly from the substrate. The gate electrode straddles the semiconductor fin. The pair of gate spacers is on opposite sidewalls of the gate electrode. The dielectric cap is atop the gate electrode and laterally between the pair of gate spacers. The hard mask layer is atop the dielectric cap and laterally between the pair of gate spacers. A bottommost position of the hard mask layer is not lower than a topmost position of the dielectric cap.Type: GrantFiled: July 24, 2020Date of Patent: August 23, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Chen Lo, Li-Te Lin, Pinyen Lin
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Patent number: 11417751Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a plurality of first semiconductor layers and a plurality of second semiconductor layers on a substrate, and the first semiconductor layers and the second semiconductor layers are alternately stacked. The method also includes forming a dummy gate structure over the first semiconductor layers and the second semiconductor layers. The method further includes removing a portion of the first semiconductor layers and second semiconductor layers to form a trench, and removing the second semiconductor layers to form a recess between two adjacent first semiconductor layers. The method includes forming a dummy dielectric layer in the recess, and removing a portion of the dummy dielectric layer to form a cavity. The method also includes forming an inner spacer layer in the cavity.Type: GrantFiled: April 1, 2020Date of Patent: August 16, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tze-Chung Lin, Han-Yu Lin, Li-Te Lin, Pinyen Lin
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Patent number: 11373878Abstract: A technique for semiconductor manufacturing is provided. The technique includes the operations as follows. A semiconductor structure having a first material and a second material is revived. The first material has a first incubation time to a first etching chemistry. The second material has a second incubation time to the first etching chemistry. The first incubation time is shorter than the second incubation time. A first main etch to the semiconductor structure for a first duration by the first etching chemistry is performed. The first duration is greater than the first incubation time and shorter than the second incubation time.Type: GrantFiled: January 20, 2021Date of Patent: June 28, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Han-Yu Lin, Li-Te Lin, Tze-Chung Lin, Fang-Wei Lee, Yi-Lun Chen, Jung-Hao Chang, Yi-Chen Lo, Fo-Ju Lin, Kenichi Sano, Pinyen Lin
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Publication number: 20220181212Abstract: The present disclosure relates to a method for forming a semiconductor structure includes depositing a dielectric layer on a substrate and depositing a patterning layer on the dielectric layer. The method also includes performing a first etching process on the patterning layer to form a first region including a first plurality of blocks at a first pattern density and a second region including a second plurality of blocks at a second pattern density that is lower than the first pattern density. The method also includes performing a second etching process on the second plurality of blocks to decrease a width of each block of the second plurality of blocks and etching the dielectric layer and the substrate using the first and second pluralities of blocks to form a plurality of fin structures.Type: ApplicationFiled: February 28, 2022Publication date: June 9, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei-Lun Chen, Li-Te Lin, Chao-Hsien Huang
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Patent number: 11351635Abstract: A semiconductor fabrication apparatus includes a source chamber being operable to generate charged particles; and a processing chamber integrated with the source chamber and configured to receive the charged particles from the source chamber. The processing chamber includes a wafer stage being operable to secure and move a wafer, and a laser-charged particles interaction module that further includes a laser source to generate a first laser beam; a beam splitter configured to split the first laser beam into a second laser beam and a third laser beam; and a mirror configured to reflect the third laser beam such that the third laser beam is redirected to intersect with the second laser beam to form a laser interference pattern at a path of the charged particles, and wherein the laser interference pattern modulates the charged particles by in a micron-zone mode for processing the wafer using the modulated charged particles.Type: GrantFiled: October 15, 2019Date of Patent: June 7, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chansyun David Yang, Li-Te Lin, Pinyen Lin
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Publication number: 20220173224Abstract: A method includes forming a fin structure including a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked over a substrate. A dummy gate structure is formed across the fin structure. The exposed second portions of the fin structure are removed. A selective etching process is performed, using a gas mixture including a hydrogen-containing gas and a fluorine-containing gas, to laterally recess the first semiconductor layers. Inner spacers are formed on opposite end surfaces of the laterally recessed first semiconductor layers. Source/drain epitaxial structures are formed on opposite end surfaces of the second semiconductor layers. The dummy gate structure is removed to expose the first portion of the fin structure. The laterally recessed first semiconductor layers are removed. A gate structure is formed to surround each of the second semiconductor layers.Type: ApplicationFiled: January 19, 2021Publication date: June 2, 2022Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC Nanjing Company LimitedInventors: Han-Yu LIN, Fang-Wei LEE, Kai-Tak LAM, Raghunath PUTIKAM, Tzer-Min SHEN, Li-Te LIN, Pinyen LIN, Cheng-Tzu YANG, Tzu-Li LEE, Tze-Chung LIN
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Publication number: 20220157605Abstract: A method of manufacturing a semiconductor device including operations of forming a first hard mask over an underlying layer on a substrate by a photolithographic and etching method, forming a sidewall spacer pattern having a first sidewall portion and a second sidewall portion on opposing sides of the first hard mask, etching the first sidewall portion, etching the first hard mask and leaving the second sidewall portion bridging a gap of the etched first hard mask, and processing the underlying layer using the second hard mask.Type: ApplicationFiled: January 31, 2022Publication date: May 19, 2022Inventors: Shih-Chun HUANG, Chiu-Hsiang CHEN, Ya-Wen YEH, Yu-Tien SHEN, Po-Chin CHANG, Chien-Wen LAI, Wei-Liang LIN, Ya Hui CHANG, Yung-Sung YEN, Li-Te LIN, Pinyen LIN, Ru-Gun LIU, Chin-Hsiang LIN
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Publication number: 20220157648Abstract: An equipment includes a supporter and an etching device. The supporter is configured to support a semiconductor device. The semiconductor device includes an etch stop layer, a material layer, and a mask layer. The mask layer has openings to expose portions of the material layer. The etching device is configured to emit a plurality of directional charged particle beams to etch the exposed portions of the material layer for forming gaps in the material layer, in which the etching device has plural ion extraction apertures to emit the directional charged particle beams. A vertical distance between the semiconductor device and the ion extraction apertures is determined in accordance with a profile of each of the gap, each of the directional charged particle beams has two energy peaks at two angles, and the angles are determined in accordance with a profile of each of the gaps and the vertical distance.Type: ApplicationFiled: February 7, 2022Publication date: May 19, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chan-Syun David YANG, Li-Te LIN, Yu-Ming LIN
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Publication number: 20220130693Abstract: The present disclosure provides a semiconductor fabrication apparatus. The semiconductor apparatus includes a processing chamber for etching; a substrate stage integrated in the processing chamber and being configured to secure a semiconductor wafer; a reflective mirror configured inside the processing chamber to reflect thermal energy from the heating mechanism toward the semiconductor wafer; and a heating mechanism embedded in the process chamber and is operable to perform a baking process to remove a by-product generated during the etching. The heating mechanism is integrated between the reflective mirror and a gas distribution plate of the processing chamber.Type: ApplicationFiled: January 10, 2022Publication date: April 28, 2022Inventors: Han-Yu Lin, Yi-Ruei Jhan, Fang-Wei Lee, Li-Te Lin, Pinyen Lin, Tze-Chung Lin
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Publication number: 20220093469Abstract: A method for fabricating a semiconductor arrangement includes performing a first etching of a semiconductive structure to expose a first portion of a sidewall of a first layer adjacent the semiconductive structure. The first etching forms a first protective layer on the first portion of the sidewall of the first layer, and the first protective layer is formed from a first accumulation of by-product material formed from an etchant of the first etching interacting with the semiconductive structure. The method includes performing a first flash to remove at least some of the first protective layer.Type: ApplicationFiled: December 6, 2021Publication date: March 24, 2022Inventors: Wei-Lun Chen, Chao-Hsien HUANG, Li-Te LIN, Pinyen LIN