Patents by Inventor Li-Ting Chen
Li-Ting Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240150592Abstract: Provided is a photocurable conductive black composition including: (a) at least one (meth)acrylate-functionalized urethane oligomer; (b) at least one photopolymerizable compound; (c) a photoinitiator; (d) a visible-light blocking system; (e) conductive fillers; and optionally (f) a thermal initiator. Also provided are a method for forming a cured product composed of the photocurable conductive black compositions, and an article comprising the cured product.Type: ApplicationFiled: October 24, 2023Publication date: May 9, 2024Inventors: Chien-Ho HUANG, Yi-Ting CHEN, Tsung-Han TSAI, Li-Yen LIN
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Publication number: 20240145867Abstract: A separator for a lithium battery and a method for manufacturing the same are provided. The separator includes a substrate layer and a coating layer. The substrate layer is a polyolefin porous film and has a substrate thickness ranging from 10 to 30 micrometers. The coating layer is coated on the substrate layer, and has a coating layer thickness ranging from 1 to 5 micrometers. The coating layer includes a heat-resistant resin material and a plurality of inorganic ceramic particles glued in the heat-resistant resin material. The heat-resistant resin material has a melting point (Tm) or a glass transition temperature (Tg) of not less than 150° C. An average particle size of the inorganic ceramic particles is 10% to 40% of the coating layer thickness of the coating layer. The inorganic ceramic particles are stacked in the coating layer with a height of at least three layers.Type: ApplicationFiled: January 17, 2023Publication date: May 2, 2024Inventors: TE-CHAO LIAO, CHUN-CHE TSAO, CHENG-HUNG CHEN, LI-TING WANG
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Publication number: 20240128324Abstract: A field effect transistor includes a substrate having a transistor forming region thereon; an insulating layer on the substrate; a first graphene layer on the insulating layer within the transistor forming region; an etch stop layer on the first graphene layer within the transistor forming region; a first inter-layer dielectric layer on the etch stop layer; a gate trench recessed into the first inter-layer dielectric layer and the etch stop layer within the transistor forming region; a second graphene layer on interior surface of the gate trench; a gate dielectric layer on the second graphene layer and on the first inter-layer dielectric layer; and a gate electrode on the gate dielectric layer within the gate trench.Type: ApplicationFiled: November 21, 2022Publication date: April 18, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Kuo-Chih Lai, Shih-Min Chou, Nien-Ting Ho, Wei-Ming Hsiao, Li-Han Chen, Szu-Yao Yu, Chung-Yi Chiu
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Patent number: 11955553Abstract: Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.Type: GrantFiled: February 24, 2023Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Su-Hao Liu, Kuo-Ju Chen, Wen-Yen Chen, Ying-Lang Wang, Liang-Yin Chen, Li-Ting Wang, Huicheng Chang
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Publication number: 20240088225Abstract: A method includes forming a gate stack on a first portion of a semiconductor substrate, removing a second portion of the semiconductor substrate on a side of the gate stack to form a recess, growing a semiconductor region starting from the recess, implanting the semiconductor region with an impurity, and performing a melt anneal on the semiconductor region. At least a portion of the semiconductor region is molten during the melt anneal.Type: ApplicationFiled: November 14, 2023Publication date: March 14, 2024Inventors: Su-Hao Liu, Wen-Yen Chen, Li-Heng Chen, Li-Ting Wang, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo, Ying-Lang Wang
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Patent number: 11916131Abstract: According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the protrusion; laterally etching a sidewall of the etch stop layer; forming an insulating layer over the etch stop layer; forming a film layer over the insulating layer and the etch stop layer; performing chemical mechanical polishing on the film layer and exposing the etch stop layer; etching a portion of the etch stop layer to expose a top surface of the protrusion; forming an oxide layer over the protrusion and the film layer; and performing chemical mechanical polishing on the oxide layer and exposing the film layer.Type: GrantFiled: November 4, 2020Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: De-Fang Chen, Teng-Chun Tsai, Cheng-Tung Lin, Li-Ting Wang, Chun-Hung Lee, Ming-Ching Chang, Huan-Just Lin
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Publication number: 20230253470Abstract: A semiconductor structure includes a semiconductor substrate; fin active regions protruded above the semiconductor substrate; and a gate stack disposed on the fin active regions; wherein the gate stack includes a high-k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer. The gate stack has an uneven profile in a sectional view with a first dimension D1 at a top surface, a second dimension D2 at a bottom surface, and a third dimension D3 at a location between the top surface and the bottom surface, and wherein each of D1 and D2 is greater than D3.Type: ApplicationFiled: April 17, 2023Publication date: August 10, 2023Inventors: Chi-Sheng Lai, Yu-Fan Peng, Li-Ting Chen, Yu-Shan Lu, Yu-Bey Wu, Wei-Chung Sun, Yuan-Ching Peng, Kuei-Yu Kao, Shih-Yao Lin, Chih-Han Lin, Pei-Yi Liu, Jing Yi Yan
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Patent number: 11652003Abstract: Processes to form differently-pitched gate structures are provided. An example method includes providing a workpiece having a substrate and semiconductor fins spaced apart from one another by an isolation feature, depositing a gate material layer over the workpiece, forming a patterned hard mask over the gate material layer, the patterned hard mask including differently-pitched elongated features, performing a first etch process using the patterned hard mask as an etch mask through the gate material layer to form a trench, performing a second etch process using the patterned hard mask as an etch mask to extend the trench to a top surface of the isolation feature, and performing a third etch process using the patterned hard mask to extend the trench into the isolation feature. The first etch process includes use of carbon tetrafluoride and is free of use of oxygen gas.Type: GrantFiled: February 28, 2022Date of Patent: May 16, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chi-Sheng Lai, Wei-Chung Sun, Li-Ting Chen, Kuei-Yu Kao, Chih-Han Lin
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Patent number: 11631745Abstract: A semiconductor structure includes a semiconductor substrate; fin active regions protruded above the semiconductor substrate; and a gate stack disposed on the fin active regions; wherein the gate stack includes a high-k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer. The gate stack has an uneven profile in a sectional view with a first dimension D1 at a top surface, a second dimension D2 at a bottom surface, and a third dimension D3 at a location between the top surface and the bottom surface, and wherein each of D1 and D2 is greater than D3.Type: GrantFiled: April 2, 2021Date of Patent: April 18, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chi-Sheng Lai, Yu-Fan Peng, Li-Ting Chen, Yu-Shan Lu, Yu-Bey Wu, Wei-Chung Sun, Yuan-Ching Peng, Kuei-Yu Kao, Shih-Yao Lin, Chih-Han Lin, Pei-Yi Liu, Jing Yi Yan
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Patent number: 11557590Abstract: A device includes a plurality of fin structures that each protrude vertically upwards out of a substrate and each extend in a first direction in a top view. A gate structure is disposed over the fin structures. The gate structure extends in a second direction in the top view. The second direction is different from the first direction. The fin structures have a fin pitch equal to a sum of: a dimension of one of the fin structures in the second direction and a distance between an adjacent pair of the fin structures in the second direction. An end segment of the gate structure extends beyond an edge of a closest one of the fin structures in the second direction. The end segment has a tapered profile in the top view or is at least 4 times as long as the fin pitch in the second direction.Type: GrantFiled: June 11, 2020Date of Patent: January 17, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chi-Sheng Lai, Wei-Chung Sun, Li-Ting Chen, Kuei-Yu Kao, Chih-Han Lin
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Publication number: 20220359511Abstract: A device includes a plurality of fin structures that each protrude vertically upwards out of a substrate and each extend in a first direction in a top view. A gate structure is disposed over the fin structures. The gate structure extends in a second direction in the top view. The second direction is different from the first direction. The fin structures have a fin pitch equal to a sum of: a dimension of one of the fin structures in the second direction and a distance between an adjacent pair of the fin structures in the second direction. An end segment of the gate structure extends beyond an edge of a closest one of the fin structures in the second direction. The end segment has a tapered profile in the top view or is at least 4 times as long as the fin pitch in the second direction.Type: ApplicationFiled: July 27, 2022Publication date: November 10, 2022Inventors: Chi-Sheng Lai, Wei-Chung Sun, Li-Ting Chen, Kuei-Yu Kao, Chih-Han Lin
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Publication number: 20220328420Abstract: An alignment structure for a semiconductor device and a method of forming same are provided. A method includes forming an isolation region over a substrate and forming an alignment structure over the isolation region. Forming the alignment structure includes forming a sacrificial gate electrode layer over the substrate and the isolation region. The sacrificial gate electrode layer is patterned to form a plurality of first sacrificial gates over the isolation region. At least one of the plurality of first sacrificial gates is reshaped. The at least one of the plurality of first sacrificial gates is disposed at an edge of the alignment structure in a plan view. A sidewall of the at least one of the plurality of first sacrificial gates comprises a notch at an interface between the at least one of the plurality of first sacrificial gates and the isolation region.Type: ApplicationFiled: June 29, 2022Publication date: October 13, 2022Inventors: Chi-Sheng Lai, Wei-Chung Sun, Li-Ting Chen, Kuei-Yu Kao, Chih-Han Lin
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Patent number: 11430190Abstract: A virtual and real image fusion method is disclosed. The method comprises the following operations: obtaining a picture of a three dimensional space by a first camera, in which the picture comprises a screen picture and a tag picture of an entity tag and the screen picture is projected on the entity tag; obtaining a corresponding point data of the entity tag on the screen picture according to the picture by a processor; obtaining a spatial correction parameter according to the corresponding point data by the processor; and displaying an image on the screen picture according to the spatial correction parameter by the processor.Type: GrantFiled: January 13, 2021Date of Patent: August 30, 2022Assignee: INSTITUTE FOR INFORMATION INDUSTRYInventors: Li-Ting Chen, Ming-Fang Weng
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Patent number: 11393769Abstract: An alignment structure for a semiconductor device and a method of forming same are provided. A method includes forming an isolation region over a substrate and forming an alignment structure over the isolation region. Forming the alignment structure includes forming a sacrificial gate electrode layer over the substrate and the isolation region. The sacrificial gate electrode layer is patterned to form a plurality of first sacrificial gates over the isolation region. At least one of the plurality of first sacrificial gates is reshaped. The at least one of the plurality of first sacrificial gates is disposed at an edge of the alignment structure in a plan view. A sidewall of the at least one of the plurality of first sacrificial gates comprises a notch at an interface between the at least one of the plurality of first sacrificial gates and the isolation region.Type: GrantFiled: May 8, 2020Date of Patent: July 19, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Sheng Lai, Wei-Chung Sun, Li-Ting Chen, Kuei-Yu Kao, Chih-Han Lin
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Publication number: 20220181215Abstract: Processes to form differently-pitched gate structures are provided. An example method includes providing a workpiece having a substrate and semiconductor fins spaced apart from one another by an isolation feature, depositing a gate material layer over the workpiece, forming a patterned hard mask over the gate material layer, the patterned hard mask including differently-pitched elongated features, performing a first etch process using the patterned hard mask as an etch mask through the gate material layer to form a trench, performing a second etch process using the patterned hard mask as an etch mask to extend the trench to a top surface of the isolation feature, and performing a third etch process using the patterned hard mask to extend the trench into the isolation feature. The first etch process includes use of carbon tetrafluoride and is free of use of oxygen gas.Type: ApplicationFiled: February 28, 2022Publication date: June 9, 2022Inventors: Chi-Sheng Lai, Wei-Chung Sun, Li-Ting Chen, Kuei-Yu Kao, Chih-Han Lin
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Publication number: 20220114789Abstract: A virtual and real image fusion method is disclosed. The method comprises the following operations: obtaining a picture of a three dimensional space by a first camera, in which the picture comprises a screen picture and a tag picture of an entity tag and the screen picture is projected on the entity tag; obtaining a corresponding point data of the entity tag on the screen picture according to the picture by a processor; obtaining a spatial correction parameter according to the corresponding point data by the processor; and displaying an image on the screen picture according to the spatial correction parameter by the processor.Type: ApplicationFiled: January 13, 2021Publication date: April 14, 2022Inventors: Li-Ting CHEN, Ming-Fang WENG
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Patent number: 11264282Abstract: Processes to form differently-pitched gate structures are provided. An example method includes providing a workpiece having a substrate and semiconductor fins spaced apart from one another by an isolation feature, depositing a gate material layer over the workpiece, forming a patterned hard mask over the gate material layer, the patterned hard mask including differently-pitched elongated features, performing a first etch process using the patterned hard mask as an etch mask through the gate material layer to form a trench, performing a second etch process using the patterned hard mask as an etch mask to extend the trench to a top surface of the isolation feature, and performing a third etch process using the patterned hard mask to extend the trench into the isolation feature. The first etch process includes use of carbon tetrafluoride and is free of use of oxygen gas.Type: GrantFiled: February 25, 2020Date of Patent: March 1, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chi-Sheng Lai, Wei-Chung Sun, Li-Ting Chen, Kuei-Yu Kao, Chih-Han Lin
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Publication number: 20210359095Abstract: A semiconductor structure includes a semiconductor substrate; fin active regions protruded above the semiconductor substrate; and a gate stack disposed the fin active regions; wherein the gate stack includes a high-k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer. The gate stack has an uneven profile in a sectional view with a first dimension D1 at a top surface, a second dimension D2 at a bottom surface, and a third dimension D3 at a location between the top surface and the bottom surface, and wherein each of D1 and D2 is greater than D3.Type: ApplicationFiled: April 2, 2021Publication date: November 18, 2021Inventors: Chi-Sheng Lai, Yu-Fan Peng, Li-Ting Chen, Yu-Shan Lu, Yu-Bey Wu, Wei-Chung Sun, Yuan-Ching Peng, Kuei-Yu Kao, Shih-Yao Lin, Chih-Han Lin, Pei-Yi Liu, Jing Yi Yan
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Publication number: 20210265219Abstract: Processes to form differently-pitched gate structures are provided. An example method includes providing a workpiece having a substrate and semiconductor fins spaced apart from one another by an isolation feature, depositing a gate material layer over the workpiece, forming a patterned hard mask over the gate material layer, the patterned hard mask including differently-pitched elongated features, performing a first etch process using the patterned hard mask as an etch mask through the gate material layer to form a trench, performing a second etch process using the patterned hard mask as an etch mask to extend the trench to a top surface of the isolation feature, and performing a third etch process using the patterned hard mask to extend the trench into the isolation feature. The first etch process includes use of carbon tetrafluoride and is free of use of oxygen gas.Type: ApplicationFiled: February 25, 2020Publication date: August 26, 2021Inventors: Chi-Sheng Lai, Wei-Chung Sun, Li-Ting Chen, Kuei-Yu Kao, Chih-Han Lin
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Publication number: 20210257359Abstract: A device includes a plurality of fin structures that each protrude vertically upwards out of a substrate and each extend in a first direction in a top view. A gate structure is disposed over the fin structures. The gate structure extends in a second direction in the top view. The second direction is different from the first direction. The fin structures have a fin pitch equal to a sum of: a dimension of one of the fin structures in the second direction and a distance between an adjacent pair of the fin structures in the second direction. An end segment of the gate structure extends beyond an edge of a closest one of the fin structures in the second direction. The end segment has a tapered profile in the top view or is at least 4 times as long as the fin pitch in the second direction.Type: ApplicationFiled: June 11, 2020Publication date: August 19, 2021Inventors: Chi-Sheng Lai, Wei-Chung Sun, Li-Ting Chen, Kuei-Yu Kao, Chih-Han Lin