Patents by Inventor Li-Ting Wang
Li-Ting Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145867Abstract: A separator for a lithium battery and a method for manufacturing the same are provided. The separator includes a substrate layer and a coating layer. The substrate layer is a polyolefin porous film and has a substrate thickness ranging from 10 to 30 micrometers. The coating layer is coated on the substrate layer, and has a coating layer thickness ranging from 1 to 5 micrometers. The coating layer includes a heat-resistant resin material and a plurality of inorganic ceramic particles glued in the heat-resistant resin material. The heat-resistant resin material has a melting point (Tm) or a glass transition temperature (Tg) of not less than 150° C. An average particle size of the inorganic ceramic particles is 10% to 40% of the coating layer thickness of the coating layer. The inorganic ceramic particles are stacked in the coating layer with a height of at least three layers.Type: ApplicationFiled: January 17, 2023Publication date: May 2, 2024Inventors: TE-CHAO LIAO, CHUN-CHE TSAO, CHENG-HUNG CHEN, LI-TING WANG
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Patent number: 11955553Abstract: Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.Type: GrantFiled: February 24, 2023Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Su-Hao Liu, Kuo-Ju Chen, Wen-Yen Chen, Ying-Lang Wang, Liang-Yin Chen, Li-Ting Wang, Huicheng Chang
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Publication number: 20240088225Abstract: A method includes forming a gate stack on a first portion of a semiconductor substrate, removing a second portion of the semiconductor substrate on a side of the gate stack to form a recess, growing a semiconductor region starting from the recess, implanting the semiconductor region with an impurity, and performing a melt anneal on the semiconductor region. At least a portion of the semiconductor region is molten during the melt anneal.Type: ApplicationFiled: November 14, 2023Publication date: March 14, 2024Inventors: Su-Hao Liu, Wen-Yen Chen, Li-Heng Chen, Li-Ting Wang, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo, Ying-Lang Wang
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Patent number: 11916131Abstract: According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the protrusion; laterally etching a sidewall of the etch stop layer; forming an insulating layer over the etch stop layer; forming a film layer over the insulating layer and the etch stop layer; performing chemical mechanical polishing on the film layer and exposing the etch stop layer; etching a portion of the etch stop layer to expose a top surface of the protrusion; forming an oxide layer over the protrusion and the film layer; and performing chemical mechanical polishing on the oxide layer and exposing the film layer.Type: GrantFiled: November 4, 2020Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: De-Fang Chen, Teng-Chun Tsai, Cheng-Tung Lin, Li-Ting Wang, Chun-Hung Lee, Ming-Ching Chang, Huan-Just Lin
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Patent number: 11855146Abstract: A method includes forming a gate stack on a first portion of a semiconductor substrate, removing a second portion of the semiconductor substrate on a side of the gate stack to form a recess, growing a semiconductor region starting from the recess, implanting the semiconductor region with an impurity, and performing a melt anneal on the semiconductor region. At least a portion of the semiconductor region is molten during the melt anneal.Type: GrantFiled: January 17, 2022Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Su-Hao Liu, Wen-Yen Chen, Li-Heng Chen, Li-Ting Wang, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo, Ying-Lang Wang
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Publication number: 20230411168Abstract: Provided is a device including a fin structure and methods for forming such a device. A method includes forming an initial fin having a sidewall. Further, the method includes forming an additional layer of fin material over the sidewall, wherein the additional layer has a thickness. Also, the method includes adjusting the thickness of the additional layer of fin material to form a fin structure with a desired critical dimension.Type: ApplicationFiled: June 16, 2022Publication date: December 21, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Yang Lu, Tz-Shian Chen, Li-Ting Wang, Huicheng Chang, Yee-Chia Yeo
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Publication number: 20230387251Abstract: A method for manufacturing a semiconductor device includes: forming a patterned structure on a substrate, the patterned structure including a dielectric layer and a dummy gate structure disposed in the dielectric layer; and subjecting the patterned structure to an ion implantation process so as to modulate a profile of the dummy gate structure.Type: ApplicationFiled: May 25, 2022Publication date: November 30, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tien-Shun CHANG, Kuo-Ju CHEN, Sih-Jie LIU, Wei-Fu WANG, Yi-Chao WANG, Li-Ting WANG, Su-Hao LIU, Huicheng CHANG, Yee-Chia YEO
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Publication number: 20230383435Abstract: In an embodiment, an apparatus includes a first pyrometer and a second pyrometer configured to monitor thermal radiation from a first point and a second point on a backside of a wafer, respectively, a first heating source in a first region and a second heating source in a second region of an epitaxial growth chamber, respectively, where a first controller adjusts an output of the first heating source and the second heating source based upon the monitored thermal radiation from the first point and the second point, respectively, a third pyrometer and a fourth pyrometer configured to monitor thermal radiation from a third point and a fourth point on a frontside of the wafer, respectively, where a second controller adjusts a flow rate of one or more precursors injected into the epitaxial growth chamber based upon the monitored thermal radiation from the first, second, third, and fourth points.Type: ApplicationFiled: August 10, 2023Publication date: November 30, 2023Inventors: Li-Ting Wang, Jung-Jen Chen, Ming-Hua Yu, Yee-Chia Yeo
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Publication number: 20230377915Abstract: An intensity of a power laser beam applied to a semiconductor device is adjusted. An applied intensity of the power laser beam is indicative of a magnitude at which the power laser beam is emitted toward the semiconductor device and a reflection intensity of a probing laser beam applied to the semiconductor device is indicative of an emissivity of the semiconductor device. The reflection intensity of the probing laser beam is measured to determine the emissivity of the semiconductor device and the applied intensity of the power laser beam is adjusted as a function of the emissivity.Type: ApplicationFiled: May 17, 2022Publication date: November 23, 2023Inventors: Wei-Fu Wang, Yi-Chao Yi-Chao, Li-Ting Wang, Yee-Chia Yeo
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Publication number: 20230377884Abstract: A method of forming a semiconductor device includes removing a light-sensitive material from a workpiece utilizing polarized electromagnetic radiation and annealing features on the workpiece utilizing electromagnetic radiation polarized in a different direction than the polarized electromagnetic radiation utilized to remove the light-sensitive material. In some embodiments, the electromagnetic radiation used to anneal the features on the workpiece is not polarized. In some described embodiments, light-sensitive material removed from the workpiece is exhausted from the chamber in which the light-sensitive removal process is carried out before it can deposit on surfaces of the chamber.Type: ApplicationFiled: May 19, 2022Publication date: November 23, 2023Inventors: Tz-Shian CHEN, Li-Ting WANG, Yee-Chia YEO
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Patent number: 11800857Abstract: A liver lesion-mouse model which is a liver-specific ISX gene expression and p53 gene knockout transgenic mouse, wherein liver lesion develops after the mouse is fed with a high calorie diet.Type: GrantFiled: October 2, 2019Date of Patent: October 31, 2023Assignee: Kaohsiung Medical UniversityInventors: Shih-Hsien Hsu, Li-Ting Wang, Shen-Nien Wang, Kwei-Yan Liu
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Publication number: 20230282706Abstract: In an embodiment, a device includes: a gate structure on a channel region of a substrate; a gate mask on the gate structure, the gate mask including a first dielectric material and an impurity, a concentration of the impurity in the gate mask decreasing in a direction extending from an upper region of the gate mask to a lower region of the gate mask; a gate spacer on sidewalls of the gate mask and the gate structure, the gate spacer including the first dielectric material and the impurity, a concentration of the impurity in the gate spacer decreasing in a direction extending from an upper region of the gate spacer to a lower region of the gate spacer; and a source/drain region adjoining the gate spacer and the channel region.Type: ApplicationFiled: May 15, 2023Publication date: September 7, 2023Inventors: Wei-Ting Chien, Wen-Yen Chen, Li-Ting Wang, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang
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Publication number: 20230215758Abstract: A method includes forming a first protruding fin and a second protruding fin over a base structure, with a trench located between the first protruding fin and the second protruding fin, depositing a trench-filling material extending into the trench, and performing a laser reflow process on the trench-filling material. In the reflow process, the trench-filling material has a temperature higher than a first melting point of the trench-filling material, and lower than a second melting point of the first protruding fin and the second protruding fin. After the laser reflow process, the trench-filling material is solidified. The method further includes patterning the trench-filling material, with a remaining portion of the trench-filling material forming a part of a gate stack, and forming a source/drain region on a side of the gate stack.Type: ApplicationFiled: March 13, 2023Publication date: July 6, 2023Inventors: Wen-Yen Chen, Li-Ting Wang, Wan-Chen Hsieh, Bo-Cyuan Lu, Tai-Chun Huang, Huicheng Chang, Yee-Chia Yeo
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Patent number: 11695042Abstract: In an embodiment, a device includes: a gate structure on a channel region of a substrate; a gate mask on the gate structure, the gate mask including a first dielectric material and an impurity, a concentration of the impurity in the gate mask decreasing in a direction extending from an upper region of the gate mask to a lower region of the gate mask; a gate spacer on sidewalls of the gate mask and the gate structure, the gate spacer including the first dielectric material and the impurity, a concentration of the impurity in the gate spacer decreasing in a direction extending from an upper region of the gate spacer to a lower region of the gate spacer; and a source/drain region adjoining the gate spacer and the channel region.Type: GrantFiled: June 10, 2021Date of Patent: July 4, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wei-Ting Chien, Wen-Yen Chen, Li-Ting Wang, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang
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Publication number: 20230197852Abstract: Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.Type: ApplicationFiled: February 24, 2023Publication date: June 22, 2023Inventors: Su-Hao Liu, Kuo-Ju Chen, Wen-Yen Chen, Ying-Lang Wang, Liang-Yin Chen, Li-Ting Wang, Huicheng Chang
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Publication number: 20230114216Abstract: A semiconductor device and a method of forming the same are provided. A method includes forming a fin structure on a substrate. The fin structure includes a plurality of first nanostructures and a plurality of second nanostructures alternately stacked. A dummy gate is formed along sidewalls and a top surface of the fin structure. A portion of the fin structure exposed by the dummy gate is recessed to form a first recess. An epitaxial source/drain region is formed in the first recess. Dopant atoms within the epitaxial source/drain region are driven into the plurality of second nanostructures. The dummy gate and the plurality of first nanostructures are removed. A replacement gate is formed wrapping around the plurality of second nanostructures.Type: ApplicationFiled: May 13, 2022Publication date: April 13, 2023Inventors: Yi-Yun Li, Tsai-Yu Huang, Li-Ting Wang, Huicheng Chang, Yee-Chia Yeo
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Patent number: 11605635Abstract: In an embodiment, a method includes forming a plurality of fins adjacent to a substrate, the plurality of fins comprising a first fin, a second fin, and a third fin; forming a first insulation material adjacent to the plurality of fins; reducing a thickness of the first insulation material; after reducing the thickness of the first insulation material, forming a second insulation material adjacent to the first insulation material and the plurality of fins; and recessing the first insulation material and the second insulation material to form a first shallow trench isolation (STI) region.Type: GrantFiled: February 26, 2021Date of Patent: March 14, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Szu-Ying Chen, Sen-Hong Syue, Li-Ting Wang, Huicheng Chang, Yee-Chia Yeo
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Patent number: 11605555Abstract: A method includes forming a first protruding fin and a second protruding fin over a base structure, with a trench located between the first protruding fin and the second protruding fin, depositing a trench-filling material extending into the trench, and performing a laser reflow process on the trench-filling material. In the reflow process, the trench-filling material has a temperature higher than a first melting point of the trench-filling material, and lower than a second melting point of the first protruding fin and the second protruding fin. After the laser reflow process, the trench-filling material is solidified. The method further includes patterning the trench-filling material, with a remaining portion of the trench-filling material forming a part of a gate stack, and forming a source/drain region on a side of the gate stack.Type: GrantFiled: July 27, 2020Date of Patent: March 14, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wen-Yen Chen, Li-Ting Wang, Wan-Chen Hsieh, Bo-Cyuan Lu, Tai-Chun Huang, Huicheng Chang, Yee-Chia Yeo
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Publication number: 20230060543Abstract: A temperature measuring apparatus for measuring a temperature of a substrate is described. A light emitting source that emits light signals such as laser pulses are applied to the substrate. A detector on the other side of the light emitting source receives the reflected laser pulses. The detector further receives emission signals associated with temperature or energy density that is radiated from the surface of the substrate. The temperature measuring apparatus determines the temperature of the substrate during a thermal process using the received laser pulses and the emission signals. To improve the signal to noise ratio of the reflected laser pulses, a polarizer may be used to polarize the laser pulses to have a S polarization. The angle in which the polarized laser pulses are applied towards the substrate may also be controlled to enhance the signal to noise ratio at the detector's end.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Inventors: Tz-Shian CHEN, Yi-Chao WANG, Wen-Yen CHEN, Li-Ting WANG, Huicheng CHANG, Yee-Chia YEO
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Publication number: 20230061802Abstract: A method of manufacturing a semiconductor device includes: determining a first reflectivity of a first anneal region on a wafer; determining a second reflectivity of a second anneal region on the wafer, performing a first laser shot on the first anneal region, measuring a first temperature of the first anneal region, and performing a second laser shot on a second anneal region. A power of the first laser shot is set in accordance with the first reflectivity. A power of the second laser shot is set in accordance with the second reflectivity.Type: ApplicationFiled: August 27, 2021Publication date: March 2, 2023Inventors: Tz-Shian Chen, Li-Ting Wang, Yee-Chia Yeo