Abstract: Device, package structure and method of forming the same are disclosed. The device includes a die encapsulated by an encapsulant, a conductive structure aside the die, and a dielectric layer overlying the conductive structure. The conductive structure includes a through via in the encapsulant, a redistribution line layer overlying the through via, and a seed layer overlying the redistribution line layer. The dielectric layer includes an opening, wherein the opening exposes a surface of the conductive structure, the opening has a scallop sidewall, and an included angle between a bottom surface of the dielectric layer and a sidewall of the opening is larger than about 60 degrees.

Abstract: A semiconductor device is provided, including a first doped region of a first conductivity type configured as a first terminal of a first diode, a second doped region of a second conductivity type configured as a second terminal of the first diode, wherein the first and second doped regions are coupled to a first voltage terminal; a first well of the first conductivity type surrounding the first and second doped regions in a layout view; a third doped region of the first conductivity type configured as a first terminal, coupled to an input/output pad, of a second diode; and a second well of the second conductivity type surrounding the third doped region in the layout view. The second and third doped regions, the first well, and the second well are configured as a first electrostatic discharge path between the I/O pad and the first voltage terminal.

Abstract: A device includes a substrate, a first dielectric layer over the substrate, a first conductive feature in the first dielectric layer, and an etch stop layer over the first dielectric layer. The etch stop layer includes metal-doped aluminum nitride. The device further includes a second dielectric layer over the etch stop layer, and a second conductive feature in the second dielectric layer. The second conductive feature extends into the etch stop layer and contacts the first conductive feature.

Abstract: A package structure includes a first semiconductor die, a first insulating encapsulation, a thermal coupling structure, and a heat dissipating component thermally coupled to the first semiconductor die through the thermal coupling structure. The first semiconductor die includes an active side, a rear side, and a sidewall connected to the active side and the rear side. The first insulating encapsulation extends along the sidewall of the first semiconductor die and includes a first side substantially leveled with the active side, a second side opposite to the first side, and topographic features at the second side. The thermal coupling structure includes a metallic layer overlying and the rear side of the first semiconductor die and the topographic features of the first insulating encapsulation. A manufacturing method of a package structure is also provided.

Abstract: A method used in forming memory circuitry comprises forming transistors individually comprising one source/drain region and another source/drain region. A channel region is between the one and the another source/drain regions. A conductive gate is operatively proximate the channel region. Openings are formed through insulative material that is directly above the transistors and into the another source/drain regions. Individual of the openings are directly above individual of the another source/drain regions. A laterally-outer insulator material is formed in the individual openings within and below the insulative material. A laterally-inner insulator material is formed in the individual openings within and below the insulative material laterally-over the laterally-outer insulator material. The laterally-outer insulator material and the laterally-inner insulator material are directly against one another and have an interface there-between.

Abstract: The present disclosure relates to a transgenic plant cell comprising polynucleotide sequences encoding glycolate dehydrogenase, malate synthase, and an inhibitory polynucleotide targeting an endogenous glycolate transporter Plgg1, wherein expression of endogenous glycolate transporter Plgg1 in the transgenic plant cell is about 20% to 80% of expression of endogenous glycolate transporter Plgg1 in a plant cell that is not transformed with an inhibitory polynucleotide targeting an endogenous glycolate transporter Plgg1. Also disclosed are transgenic plants, transgenic plant cultures, and methods for increasing photosynthesis efficiency in plants. The disclosed methods enhance biomass productivity and reduce the negative impact of photorespiration and introduction of transgenic constructs on plant growth.

Abstract: A disc brake device and a bicycle. The disc brake device comprises a bicycle frame, a mounting shaft, a wheel, and a brake disc; fork pieces is fixedly connected to a frame body; the mounting shaft is fixedly connected to the fork pieces; a hub is movably connected to the mounting shaft; spokes are provided between the hub and a rim; the brake disc is fixedly connected to the hub; the brake disc and the wheel can rotate together with respect to the mounting shaft; the brake disc has an inner surface disposed facing the spokes and an outer surface disposed facing a fork piece; a first distance, in the axial direction of the mounting shaft, between the edge of the inner surface of the brake disc farthest from the hub in the radial direction of the mounting shaft and each spoke is less than or equal to 10 mm.

Abstract: A pneumatic arrow gun has a gun body, an arrow, a positioning sleeve, and a connecting wire. The arrow is for inserting into an air tube of the gun body. The positioning sleeve is temporarily mounted around the air tube, and the arrow is disposed through the positioning sleeve. The connecting wire connects the gun body to the positioning sleeve. Because the positioning sleeve is temporarily mounted around the air tube, the arrow slides forward relative to the positioning sleeve after triggering. When triggering the arrow, the connecting wire naturally dangles. When the arrow detaches from the air tube, the positioning sleeve located at a nock of the arrow due to the sliding of the arrow. Therefore, a rebound of the arrowhead is prevented. The safety and the shooting stability are ensured. Further, the arrow is easily retrieved by the connecting wire.

Abstract: A semiconductor device and method of manufacture are provided. After a patterning of a middle layer, the middle layer is removed. In order to reduce or prevent damage to other underlying layers exposed by the patterning of the middle layer and intervening layers, an inhibitor is included within an etching process in order to inhibit the amount of material removed from the underlying layers.

Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a bottom electrode layer over a substrate. A magnetic tunnel junction (MTJ) layers are formed over the bottom electrode layer. A top electrode layer is formed over the MTJ layers. The top electrode layer is patterned. After patterning the top electrode layer, one or more process cycles are performed on the MTJ layers and the bottom electrode layer. A patterned top electrode layer, patterned MTJ layers and a patterned bottom electrode layer form MTJ structures. Each of the one or more process cycles includes performing an etching process on the MTJ layers and the bottom electrode layer for a first duration and performing a magnetic treatment on the MTJ layers and the bottom electrode layer for a second duration.

Abstract: A method includes bonding a second package component to a first package component, bonding a third package component to the first package component, attaching a dummy die to the first package component, encapsulating the second package component, the third package component, and the dummy die in an encapsulant, and performing a planarization process to level a top surface of the second package component with a top surface of the encapsulant. After the planarization process, an upper portion of the encapsulant overlaps the dummy die. The dummy die is sawed-through to separate the dummy die into a first dummy die portion and a second dummy die portion. The upper portion of the encapsulant is also sawed through.

Abstract: A vehicle electronic device is provided, including a vehicle window assembly, a first signal element, and a first protective element. The vehicle window assembly comprises a first protective substrate, a second protective substrate, and a display panel. The display panel is disposed between the first protective substrate and the second protective substrate. The first signal element is electrically connected to the display panel. The first protective element covers at least one portion of the first signal element.

Abstract: A molded electronic assembly including a circuit substrate, a plurality of electronic devices, and at least one patterned heat dissipation structure is provided. The circuit substrate includes a substrate and a circuit, where the substrate has a top surface, and the circuit has a plurality of signal contacts distributed on the top surface. The electronic devices are disposed on the circuit substrate, and each of the electronic devices has a plurality of device pins connected to the signal contacts. The at least one patterned heat dissipation structure corresponds to a signal contact of the signal contacts and starts from the corresponding signal contact and extends toward a plurality of directions on the top surface of the substrate.

Abstract: Disclosed is an electronic device, including a plurality of light-emitting units, a driving circuit, and a first comparator. The driving circuit is electrically connected to the light-emitting units. The first comparator is electrically connected to the driving circuit. The first comparator receives one of a detected power consumption value and a detected current value from the light-emitting units. The first comparator compares the one of the detected power consumption value and the detected current value with a set value and obtains a relationship therebetween to transmit a first signal. The driving circuit drives the light-emitting units according to the first signal.

Abstract: A device operates to perform acoustic echo cancellation. The device includes a speaker to output a far-end signal at the device, a microphone to receive at least a near-end signal and the far-end signal from the speaker to produce a microphone output, and an AI accelerator operative to perform neural network operations according to a first neural network model and a second neural network model to output an echo-suppressed signal. The device further includes a digital signal processing (DSP) unit. The DSP unit is operative to perform adaptive filtering to remove at least a portion of the far-end signal from the microphone output to generate a filtered near-end signal, and perform Fast Fourier Transform (FFT) and inverse FFT (IFFT) to generate input to the first neural network model and the second neural network model, respectively.

Abstract: A method includes forming a reconstructed wafer including encapsulating a device die in an encapsulant, forming a dielectric layer over the device die and the encapsulant, forming a plurality of redistribution lines extending into the dielectric layer to electrically couple to the device die, and forming a metal ring in a common process for forming the plurality of redistribution lines. The metal ring encircles the plurality of redistribution lines, and the metal ring extends into scribe lines of the reconstructed wafer. A die-saw process is performed along scribe lines of the reconstructed wafer to separate a package from the reconstructed wafer. The package includes the device die and at least a portion of the metal ring.

Abstract: A method of fabricating an integrated circuit includes placing a first set of conductive feature patterns on a first level, placing a second set of conductive feature patterns on a second level, placing a first set of via patterns between the second set of conductive feature patterns and the first set of conductive feature patterns, placing a third set of conductive feature patterns on a third level different from the first level and the second level, placing a second set of via patterns between the third set of conductive feature patterns and the second set of conductive feature patterns, and manufacturing the integrated circuit based on at least one of the above patterns of the integrated circuit.

Abstract: An electroporation system including one or more of a pipette, a pipette tip, a pipette docking assembly, and a pulse generator. The pipette docking assembly includes a pipette station, a pipette station guard, and a reservoir (e.g., a buffer tube). A method for transfecting a cell with a payload including providing an electroporation system, providing the cell, providing the payload, introducing the cell and the payload into a pipette tip, and electroporating the cell within the pipette tip by operating the electroporation system.

Abstract: Methods and systems are presented for providing a framework to securely integrate third-party logic into electronic transaction processing workflow. Third-party programming code that implements different third-party logic may be obtained and stored in a repository. A transaction processing request is received from a third-party server, and an instance of a transaction processing module is instantiated within an operating runtime environment to process a transaction according to a workflow. When the instance of the transaction processing module has reached an interruption point, the instance of the transaction processing module is suspended, and a third-party programming code is executed within an isolated runtime environment. The third-party programming code is configured to provide an output value based on attributes of the transaction. The instance of the transaction processing module then determines whether to authorize or deny the transaction based in part on the output value.

Abstract: A method includes forming a first conductive feature over a semiconductor substrate, forming an ILD layer over the first conductive feature, patterning the ILD layer to form a trench, and forming a conductive layer over the patterned ILD layer to fill the trench. The method further includes polishing the conductive layer to form a via contact configured to interconnect the first conductive feature with a second conductive feature, where polishing the conductive layer exposes a top surface of the ILD layer, polishing the exposed top surface of the ILD layer, such that a top portion of the via contact protrudes from the exposed top surface of the ILD layer, and forming the second conductive feature over the via contact, such that the top portion of the via contact extends into the second conductive feature.