Abstract: A method of fabricating an integrated circuit includes placing a first set of conductive feature patterns on a first level, placing a second set of conductive feature patterns on a second level, placing a first set of via patterns between the second set of conductive feature patterns and the first set of conductive feature patterns, placing a third set of conductive feature patterns on a third level different from the first level and the second level, placing a second set of via patterns between the third set of conductive feature patterns and the second set of conductive feature patterns, and manufacturing the integrated circuit based on at least one of the above patterns of the integrated circuit.

Abstract: An integrated circuit includes a first-voltage power rail and a second-voltage power rail in a first connection layer, and includes a first-voltage underlayer power rail and a second-voltage underlayer power rail below the first connection layer. Each of the first-voltage and second-voltage power rails extends in a second direction that is perpendicular to a first direction. Each of the first-voltage and second-voltage underlayer power rails extends in the first direction. The integrated circuit includes a first via-connector connecting the first-voltage power rail with the first-voltage underlayer power rail, and a second via-connector connecting the second-voltage power rail with the second-voltage underlayer power rail.

Abstract: Provided are semiconductor devices that include a first gate structure having a first end cap portion, a second gate structure having a second end cap portion coaxial with the first gate structure, a first dielectric region separating the first end cap portion and the second end cap portion, a first conductive element extending over the first gate structure, a second conductive element extending over the second gate structure, and a gate via electrically connecting the second gate structure and the second conductive element, with the first dielectric region having a first width and being positioned at least partially under the first conductive element and defines a spacing between the gate via and an end of the second end cap portion that exceeds a predetermined distance.

Abstract: Exemplary embodiments for an exemplary dual transmission gate and various exemplary integrated circuit layouts for the exemplary dual transmission gate are disclosed. These exemplary integrated circuit layouts represent double-height, also referred to as double rule, integrated circuit layouts. These double rule integrated circuit layouts include a first group of rows from among multiple rows of an electronic device design real estate and a second group of rows from among the multiple rows of the electronic device design real estate to accommodate a first metal layer of a semiconductor stack. The first group of rows can include a first pair of complementary metal-oxide-semiconductor field-effect (CMOS) transistors, such as a first p-type metal-oxide-semiconductor field-effect (PMOS) transistor and a first n-type metal-oxide-semiconductor field-effect (NMOS) transistor, and the second group of rows can include a second pair of CMOS transistors, such as a second PMOS transistor and a second NMOS transistor.

Abstract: The present invention pertains to a portable bag comprising a bag body, a zipper, and a strap. Particularly, the strap includes a strap loop with a blocking portion engaging thereto. Further, the blocking portion is inserted into the bag body and fixed therein by a larger outer diameter of the blocking portion than a dimension of a detaching portion while interlocking the zipper, which results in the strap to be a held in the hand or in the shoulder. As a result, the present invention provides with multiple ways for the portability and the convenience in use while carrying out the blocking portion and the articles in the bag.

Abstract: The present invention pertains to a wearable bag comprising a body divided by two panels, two shoulder straps respectively disposed on two panels, and a zipper with two zipper tracks and two zipper tabs. Particularly, the body has a plurality of pockets disposed therein, which are sewed to the front side thereof; further the panels are interlocked to form a bag with the shoulder straps by the zipper tabs sliding toward the same direction along the zipper tracks; relatively, the panels are detached to form a wearable vest while the zipper tabs slide toward a reverse direction. As a result, the present invention provides with multiple uses, used for a bag or a vest, and also facilitates to decrease the possibility of robbery for increasing the security defense.