Patents by Inventor Li-Yen Fang
Li-Yen Fang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240167185Abstract: A composite metal foil and a method of manufacturing the same are provided. The composite metal foil includes at least a first metal layer and a second metal layer. The first metal layer is copper foil, nickel foil, stainless steel foil, or a combination thereof. The second metal layer is disposed on a surface of the first metal layer. A contact angle of a surface of the second metal layer to liquid lithium metal is lower than 90 degrees.Type: ApplicationFiled: January 18, 2023Publication date: May 23, 2024Applicant: Industrial Technology Research InstituteInventors: Chiu-Yen Chiu, Li-Ju Chen, Sheng-Hui Wu, Chia-Chen Fang
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Patent number: 11158659Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes an interconnect structure formed over a substrate and a passivation layer formed over the interconnect structure. The semiconductor device structure also includes an anti-acid layer formed in the passivation layer and a bonding layer formed on the anti-acid layer and the passivation layer. The anti-acid layer has a thickness that is greater than about 140 nm.Type: GrantFiled: July 30, 2018Date of Patent: October 26, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yin-Shuo Chu, Chi-Chung Yu, Li-Yen Fang, Tain-Shang Chang, Yao-Hsiang Liang, Min-Chih Tsai
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Patent number: 10867889Abstract: A method of manufacturing a semiconductor structure includes receiving a substrate including a first side and a second side opposite to the first side; forming a recess extending between the first side and the second side; and disposing a conductive material in the recess to form a conductive via, wherein the conductive via includes an interface, a first portion adjacent to the first side and a second portion adjacent to the second side, the interface is disposed between the first portion and the second portion, an average grain size of the first portion is substantially different from an average grain size of the second portion.Type: GrantFiled: September 6, 2018Date of Patent: December 15, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Li-Yen Fang, Chih-Chang Huang, Jung-Chih Tsao, Yao-Hsiang Liang, Yu-Ku Lin
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Publication number: 20190019743Abstract: A method of manufacturing a semiconductor structure includes receiving a substrate including a first side and a second side opposite to the first side; forming a recess extending between the first side and the second side; and disposing a conductive material in the recess to form a conductive via, wherein the conductive via includes an interface, a first portion adjacent to the first side and a second portion adjacent to the second side, the interface is disposed between the first portion and the second portion, an average grain size of the first portion is substantially different from an average grain size of the second portion.Type: ApplicationFiled: September 6, 2018Publication date: January 17, 2019Inventors: LI-YEN FANG, CHIH-CHANG HUANG, JUNG-CHIH TSAO, YAO-HSIANG LIANG, YU-KU LIN
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Publication number: 20180350855Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes an interconnect structure formed over a substrate and a passivation layer formed over the interconnect structure. The semiconductor device structure also includes an anti-acid layer formed in the passivation layer and a bonding layer formed on the anti-acid layer and the passivation layer. The anti-acid layer has a thickness that is greater than about 140 nm.Type: ApplicationFiled: July 30, 2018Publication date: December 6, 2018Inventors: Yin-Shuo Chu, Chi-Chung Yu, Li-Yen Fang, Tain-Shang Chang, Yao-Hsiang Liang, Min-Chih Tsai
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Patent number: 10074594Abstract: A semiconductor structure includes a substrate including a first side, a second side opposite to the first side, and a device layer over the second side, and a conductive via extending through the substrate, and including a first portion adjacent to the first side and a second portion adjacent to the device layer, wherein the conductive via includes an interface between the first portion and the second portion, an average grain size of the first portion is substantially different from an average grain size of the second portion.Type: GrantFiled: April 17, 2015Date of Patent: September 11, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Li-Yen Fang, Chih-Chang Huang, Jung-Chih Tsao, Yao-Hsiang Liang, Yu-Ku Lin
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Patent number: 9991204Abstract: A semiconductor device includes a substrate, a dielectric structure, a barrier layer, a glue layer, a copper seed layer and a copper layer. The dielectric structure is disposed over the substrate. The dielectric structure has a through via hole passing through the dielectric structure, and a sidewall of the through via hole includes at least one indentation. The barrier layer conformally covers the sidewall and a bottom of the through via hole. The glue layer conformally covers the barrier layer. The copper seed layer conformally covers the glue layer. The copper layer covers the copper seed layer and fills the through via hole.Type: GrantFiled: June 21, 2017Date of Patent: June 5, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Li-Yen Fang, Jung-Chih Tsao, Yao-Hsiang Liang, Yu-Ku Lin
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Patent number: 9859124Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes providing a substrate with a dielectric disposed thereon, wherein the dielectric has a recess formed by a plurality of exposed surfaces; forming a conductive film on the plurality of exposed surfaces; applying a surface agent to the recess so that the surface agent adheres to a portion of the conductive film; immersing the substrate into an electroplating solution comprising metallic ions; and applying a bias to the conductive film in order to fill metallic material in the recess.Type: GrantFiled: April 17, 2015Date of Patent: January 2, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTDInventors: Li-Yen Fang, Jung-Chih Tsao, Yao-Hsiang Liang, Yu-Ku Lin
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Publication number: 20170287841Abstract: A semiconductor device includes a substrate, a dielectric structure, a barrier layer, a glue layer, a copper seed layer and a copper layer. The dielectric structure is disposed over the substrate. The dielectric structure has a through via hole passing through the dielectric structure, and a sidewall of the through via hole includes at least one indentation. The barrier layer conformally covers the sidewall and a bottom of the through via hole. The glue layer conformally covers the barrier layer. The copper seed layer conformally covers the glue layer. The copper layer covers the copper seed layer and fills the through via hole.Type: ApplicationFiled: June 21, 2017Publication date: October 5, 2017Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Li-Yen FANG, Jung-Chih TSAO, Yao-Hsiang LIANG, Yu-Ku LIN
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Patent number: 9711454Abstract: A semiconductor device includes a substrate, a dielectric structure, a barrier layer, a glue layer, a copper seed layer and a copper layer. The dielectric structure is disposed over the substrate. The dielectric structure has a through via hole passing through the dielectric structure, and a sidewall of the through via hole includes at least one indentation. The barrier layer conformally covers the sidewall and a bottom of the through via hole. The glue layer conformally covers the barrier layer. The copper seed layer conformally covers the glue layer. The copper layer covers the copper seed layer and fills the through via hole.Type: GrantFiled: August 29, 2015Date of Patent: July 18, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Li-Yen Fang, Jung-Chih Tsao, Yao-Hsiang Liang, Yu-Ku Lin
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Publication number: 20170170215Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes an interconnect structure formed over a substrate and a passivation layer formed over the interconnect structure. The semiconductor device structure also includes an anti-acid layer formed in the passivation layer and a bonding layer formed on the anti-acid layer and the passivation layer. The anti-acid layer has a thickness that is greater than about 140 nm.Type: ApplicationFiled: December 15, 2015Publication date: June 15, 2017Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yin-Shuo CHU, Chi-Chung YU, Li-Yen FANG, Tain-Shang CHANG, Yao-Hsiang LIANG, Min-Chih TSAI
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Publication number: 20170062343Abstract: A semiconductor device includes a substrate, a dielectric structure, a barrier layer, a glue layer, a copper seed layer and a copper layer. The dielectric structure is disposed over the substrate. The dielectric structure has a through via hole passing through the dielectric structure, and a sidewall of the through via hole includes at least one indentation. The barrier layer conformally covers the sidewall and a bottom of the through via hole. The glue layer conformally covers the barrier layer. The copper seed layer conformally covers the glue layer. The copper layer covers the copper seed layer and fills the through via hole.Type: ApplicationFiled: August 29, 2015Publication date: March 2, 2017Inventors: Li-Yen FANG, Jung-Chih TSAO, Yao-Hsiang LIANG, Yu-Ku LIN
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Publication number: 20160307823Abstract: A semiconductor structure includes a substrate including a first side, a second side opposite to the first side, and a device layer over the second side, and a conductive via extending through the substrate, and including a first portion adjacent to the first side and a second portion adjacent to the device layer, wherein the conductive via includes an interface between the first portion and the second portion, an average grain size of the first portion is substantially different from an average grain size of the second portion.Type: ApplicationFiled: April 17, 2015Publication date: October 20, 2016Inventors: LI-YEN FANG, CHIH-CHANG HUANG, JUNG-CHIH TSAO, YAO-HSIANG LIANG, YU-KU LIN
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Publication number: 20160307761Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes providing a substrate with a dielectric disposed thereon, wherein the dielectric has a recess formed by a plurality of exposed surfaces; forming a conductive film on the plurality of exposed surfaces; applying a surface agent to the recess so that the surface agent adheres to a portion of the conductive film; immersing the substrate into an electroplating solution comprising metallic ions; and applying a bias to the conductive film in order to fill metallic material in the recess.Type: ApplicationFiled: April 17, 2015Publication date: October 20, 2016Inventors: LI-YEN FANG, JUNG-CHIH TSAO, YAO-HSIANG LIANG, YU-KU LIN
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Patent number: 8642439Abstract: A system and method for forming a semiconductor device is provided. An embodiment comprises forming a silicide region on a substrate along with a transition region between the silicide region and the substrate. The thickness of the silicide precursor material layer along with the annealing conditions are controlled such that there is a larger ratio of one atomic species within the transition region than another atomic species, thereby increasing the hole mobility within the transition region.Type: GrantFiled: April 9, 2013Date of Patent: February 4, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jun-Nan Nian, Li-Yen Fang, Yu-Ting Lin, Shih-Chieh Chang, Yu-Ku Lin, Ying-Lang Wang
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Publication number: 20130126950Abstract: A system and method for forming a semiconductor device is provided. An embodiment comprises forming a silicide region on a substrate along with a transition region between the silicide region and the substrate. The thickness of the silicide precursor material layer along with the annealing conditions are controlled such that there is a larger ratio of one atomic species within the transition region than another atomic species, thereby increasing the hole mobility within the transition region.Type: ApplicationFiled: November 23, 2011Publication date: May 23, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jun-Nan Nian, Li-Yen Fang, Yu-Ting Lin, Shih-Chieh Chang, Yu-Ku Lin, Ying-Lang Wang
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Patent number: 8435893Abstract: A system and method for forming a semiconductor device is provided. An embodiment comprises forming a silicide region on a substrate along with a transition region between the silicide region and the substrate. The thickness of the silicide precursor material layer along with the annealing conditions are controlled such that there is a larger ratio of one atomic species within the transition region than another atomic species, thereby increasing the hole mobility within the transition region.Type: GrantFiled: November 23, 2011Date of Patent: May 7, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jun-Nan Nian, Li-Yen Fang, Yu-Ting Lin, Shih-Chieh Chang, Yu-Ku Lin, Ying-Lang Wang