Patents by Inventor Li Yi-Lin
Li Yi-Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240142935Abstract: A method for detecting workpiece based on homogeneous multi-core architecture is illustrate. The method comprises: obtaining detecting images of detecting workpieces; identifying detecting areas of the detecting workpieces in the detecting images; dividing the preset rotation angle to obtain the rotation accuracy and initial rotation angles; based on each of the initial rotation angles, rotating the detecting areas to obtain a rotation area of each of the initial rotation angles; calculating similarity values between each of the rotation areas and a preset qualified area, and determining a largest similarity value as the target similarity value; and when the rotation accuracy is greater than or equal to a preset accuracy, identifying whether the detecting workpiece is a qualified workpiece according to the target similarity value and a preset similarity threshold.Type: ApplicationFiled: February 24, 2023Publication date: May 2, 2024Inventors: CHENG-FENG WANG, LI-CHE LIN, YEN-YI LIN
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Publication number: 20240142664Abstract: Two types of blue light blocking contact lenses are provided and are formed by curing different compositions. The first composition includes a blue light blocking component formed by mixing or reacting a first hydrophilic monomer and a yellow dye, a first colored dye component formed by mixing or reacting a second hydrophilic monomer and a first colored dye, at least one third hydrophilic monomer, a crosslinker, and an initiator. The first colored dye includes a green dye, a cyan dye, a blue dye, an orange dye, a red dye, a black dye, or combinations thereof. The second composition includes a blue light blocking component, at least one hydrophilic monomer, a crosslinker, and an initiator. The blue light blocking component is formed by mixing or reacting glycerol monomethacrylate and a yellow dye. Further, methods for preparing the above contact lenses are provided.Type: ApplicationFiled: February 12, 2023Publication date: May 2, 2024Inventors: Han-Yi CHANG, Chun-Han CHEN, Tsung-Kao HSU, Wei-che WANG, Yu-Hung LIN, Wan-Ying GAO, Li-Hao LIU
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Publication number: 20240144467Abstract: A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.Type: ApplicationFiled: January 8, 2024Publication date: May 2, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Huei Chen, Pei-Chao Su, Xiaomeng Chen, Chan-Ming Chang, Shih-Yung Chen, Hung-Yi Chung, Kuang-Shing Chen, Li-Jou Lee, Yung-Cheng Lin, Wei-Chen Wu, Shih-Chang Wang, Chien-An Lin
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Patent number: 11965069Abstract: A heat-shrinkable polyester film made of a polyester-forming resin composition includes a recycled material, and has an exothermic crystallization peak and an endothermic melting peak which are determined via differential scanning calorimetry, and which satisfy relationships of T2?T1?68° C. and T3?T2?78° C., where T1 represents an onset point of the exothermic crystallization peak, T2 represents an end point of the exothermic crystallization peak and an onset point of the endothermic melting peak, and T3 represents an end point of the endothermic melting peak. A method for manufacturing the heat-shrinkable polyester film is also disclosed.Type: GrantFiled: February 5, 2021Date of Patent: April 23, 2024Assignee: FAR EASTERN NEW CENTURY CORPORATIONInventors: Li-Ling Chang, Yow-An Leu, Ting-Yu Lin, Ching-Chun Tsai, Wen-Yi Chang
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Publication number: 20240088650Abstract: In some aspects of the present disclosure, an electrostatic discharge (ESD) protection circuit is disclosed. In some aspects, the ESD protection circuit includes a first transistor coupled to a pad, a second transistor coupled between the first transistor and ground, a stack of transistors coupled to the first transistor, and an ESD clamp coupled between the stack of transistors and the ground.Type: ApplicationFiled: November 20, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: Li-Wei Chu, Tao Yi Hung, Chia-Hui Chen, Wun-Jie Lin, Jam-Wem Lee
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Patent number: 11921474Abstract: A virtual metrology method using a convolutional neural network (CNN) is provided. In this method, a dynamic time warping (DTW) algorithm is used to delete unsimilar sets of process data, and adjust the sets of process data to be of the same length, thereby enabling the CNN to be used for virtual metrology. A virtual metrology model of the embodiments of the present invention includes several CNN models and a conjecture model, in which plural inputs of the CNN model are sets of time sequence data of respective parameters, and plural outputs of the CNN models are inputs to the conjecture model.Type: GrantFiled: May 25, 2021Date of Patent: March 5, 2024Assignee: NATIONAL CHENG KUNG UNIVERSITYInventors: Fan-Tien Cheng, Yu-Ming Hsieh, Tan-Ju Wang, Li-Hsuan Peng, Chin-Yi Lin
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Patent number: 11416665Abstract: A power rail design method is disclosed that includes the steps outlined below. A plurality of power rails and a plurality of power domains corresponding thereto in an integrated circuit design file are identified. A design rule check for a plurality of circuit units in the integrated circuit design file is performed to retrieve a plurality of non-violating circuit regions that correspond to the power rails in each of the power domains. The power rails corresponding to at least part of the plurality of non-violating circuit regions in the integrated circuit design file are widened to occupy at least part of the non-violating circuit regions for the plurality of power rails.Type: GrantFiled: October 22, 2020Date of Patent: August 16, 2022Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Cheng-Chen Huang, Yun-Ru Wu, Hsin-Chang Lin, Shu-Yi Kao, Chih-Chan Chen, Chia-Jung Hsu, Li-Yi Lin
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Patent number: 11030379Abstract: Disclosed is an integrated circuit (IC) layout method capable of reducing an IR drop as a result of an IC layout process. The method includes the following steps: performing the IC layout process and obtaining an original IC layout; performing an IR drop analysis on the original IC layout and identifying an IR drop hot zone; determining a circuit density limit of the IR drop hot zone; and performing the IC layout process again according to the circuit density limit and obtaining an updated IC layout.Type: GrantFiled: July 29, 2020Date of Patent: June 8, 2021Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Tien-Kuo Lin, Li-Yi Lin, Yun-Chih Chang
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Patent number: 10997353Abstract: An IC design method is provided that includes steps outlined below. A clock tree structure is retrieved from an IC design file. A branch level number of a branch that each of clock units in the clock tree structure locates is determined. A common branch level number of a common branch that closest to each two of the flip-flops is determined. A scan chain structure is retrieved from the IC design file. A wire distance and a clock skew of each two of the flip-flops are determined. A cost is calculated according to the common branch number, the wire distance and the clock skew. An initial point and a terminal point of the flip-flops in the scan chain structure are determined to further calculate a path having a minimum cost. The order of the scan chain structure of the IC design file is updated.Type: GrantFiled: May 28, 2020Date of Patent: May 4, 2021Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: I-Ching Tsai, Li-Yi Lin, Yun-Chih Chang, Shu-Yi Kao
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Publication number: 20210124864Abstract: A power rail design method is disclosed that includes the steps outlined below. A plurality of power rails and a plurality of power domains corresponding thereto in an integrated circuit design file are identified. A design rule check for a plurality of circuit units in the integrated circuit design file is performed to retrieve a plurality of non-violating circuit regions that correspond to the power rails in each of the power domains. The power rails corresponding to at least part of the plurality of non-violating circuit regions in the integrated circuit design file are widened to occupy at least part of the non-violating circuit regions for the plurality of power rails.Type: ApplicationFiled: October 22, 2020Publication date: April 29, 2021Inventors: Cheng-Chen HUANG, Yun-Ru WU, Hsin-Chang LIN, Shu-Yi KAO, Chih-Chan CHEN, Chia-Jung HSU, Li-Yi LIN
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Patent number: 10936784Abstract: A planning method for power metal lines is provided. The planning method includes selecting a block to plan, the block including a first metal layer and a second metal layer therebelow. The first metal layer includes a plurality of first metal lines along a first direction and the second metal layer includes a plurality of second metal lines along a second direction. The block includes a length in the first direction and a width in the second direction. According to a ratio of the length and the width of the block, a line width adjustment procedure is performed to adjust a first line width of each of the first metal lines and a second line width of each of the second metal lines, so that routing congestion can be avoided without affecting the IR drop.Type: GrantFiled: December 5, 2019Date of Patent: March 2, 2021Assignee: REALTEK SEMICONDUCTOR CORP.Inventors: Hsin-Wei Pan, Li-Yi Lin, Yun-Chih Chang, Shu-Yi Kao
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Publication number: 20210034808Abstract: Disclosed is an integrated circuit (IC) layout method capable of reducing an IR drop as a result of an IC layout process. The method includes the following steps: performing the IC layout process and obtaining an original IC layout; performing an IR drop analysis on the original IC layout and identifying an IR drop hot zone; determining a circuit density limit of the IR drop hot zone; and performing the IC layout process again according to the circuit density limit and obtaining an updated IC layout.Type: ApplicationFiled: July 29, 2020Publication date: February 4, 2021Inventors: TIEN-KUO LIN, LI-YI LIN, YUN-CHIH CHANG
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Publication number: 20210004520Abstract: A planning method for power metal lines is provided. The planning method includes selecting a block to plan, the block including a first metal layer and a second metal layer therebelow. The first metal layer includes a plurality of first metal lines along a first direction and the second metal layer includes a plurality of second metal lines along a second direction. The block includes a length in the first direction and a width in the second direction. According to a ratio of the length and the width of the block, a line width adjustment procedure is performed to adjust a first line width of each of the first metal lines and a second line width of each of the second metal lines, so that routing congestion can be avoided without affecting the IR drop.Type: ApplicationFiled: December 5, 2019Publication date: January 7, 2021Applicant: REALTEK SEMICONDUCTOR CORP.Inventors: Hsin-Wei Pan, Li-Yi Lin, Yun-Chih Chang, Shu-Yi Kao
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Publication number: 20210004516Abstract: An IC design method is provided that includes steps outlined below. A clock tree structure is retrieved from an IC design file. A branch level number of a branch that each of clock units in the clock tree structure locates is determined. A common branch level number of a common branch that closest to each two of the flip-flops is determined. A scan chain structure is retrieved from the IC design file. A wire distance and a clock skew of each two of the flip-flops are determined. A cost is calculated according to the common branch number, the wire distance and the clock skew. An initial point and a terminal point of the flip-flops in the scan chain structure are determined to further calculate a path having a minimum cost. The order of the scan chain structure of the IC design file is updated.Type: ApplicationFiled: May 28, 2020Publication date: January 7, 2021Inventors: I-Ching TSAI, Li-Yi Lin, Yun-Chih Chang, Shu-Yi Kao
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Publication number: 20090064067Abstract: A method of balancing the path delay of a clock tree for minimizing clock skew of the clock tree in the IC layouts is described.Type: ApplicationFiled: August 28, 2007Publication date: March 5, 2009Applicant: Silicon Integrated Systems Corp.Inventors: Tsung-hsin Liu, Li-yi Lin
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Patent number: 7199265Abstract: This invention relates to compounds of the formula (I) which are thyroid receptor ligands, and are preferably selective for the thyroid hormone receptor ?, to methods of preparing such compounds and to methods for using such compounds such as in the regulation of metabolism.Type: GrantFiled: June 15, 2001Date of Patent: April 3, 2007Assignee: Karo Bio ABInventors: Li Yi-Lin, Johan Malm, Chris Litten, Ana Maria Garcia Collazo, Neeraj Garg
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Publication number: 20040097589Abstract: This invention relates to compounds of the formula (I) which are thyroid receptor ligands, and are preferably selective for the thyroid hormone receptor &bgr;, to methods of preparing such compounds and to methods for using such compounds such as in the regulation of metabolism.Type: ApplicationFiled: April 22, 2003Publication date: May 20, 2004Inventors: Li Yi-Lin, Johan Malm, Chris Litten, Ana Maria Garcia Collazo, Neeraj Garg