Abstract: A memory cell device includes a semiconductor nanowire extending, at a first end thereof, from a substrate; the nanowire having a doping profile so as to define a field effect transistor (FET) adjacent the first end, the FET further including a gate electrode at least partially surrounding the nanowire, the doping profile further defining a p-n junction in series with the FET, the p-n junction adjacent a second end of the nanowire; and a phase change material at least partially surrounding the nanowire, at a location corresponding to the p-n junction.

Abstract: A three-terminal switching device for use in integrated circuit devices, including a phase change material (PCM) disposed in contact between a first terminal and a second terminal; a heating device disposed in direct electrical contact between said second terminal and a third terminal, said heating device positioned proximate said PCM, and configured to switch the conductivity of a transformable portion of said PCM between a lower resistance crystalline state and a higher resistance amorphous state; and an insulating layer configured to electrically isolate said heater from said PCM material, and said heater from said first terminal.

Abstract: A switching circuit includes a plurality of three-terminal PCM switching devices connected between a voltage supply terminal and a sub-block of logic. Each of the switching devices includes a PCM disposed in contact between a first terminal and a second terminal, a heating device disposed in contact between the second terminal and a third terminal, the heating device positioned proximate the PCM, and configured to switch the conductivity of a transformable portion of the PCM between a lower resistance state and a higher resistance state; and an insulating layer configured to electrically isolate the heater from said PCM material, and the heater from the first terminal. The third terminal of a first of the PCM switching devices is coupled to a set/reset switch, and the third terminal of the remaining PCM switching devices is coupled to the second terminal of an adjacent PCM switching device in a cascade configuration.

Abstract: A coupling structure for coupling piezoelectric material generated stresses to an actuated device of an integrated circuit includes a rigid stiffener structure formed around a piezoelectric (PE) material and the actuated device, the actuated device comprising a piezoresistive (PR) material that has an electrical resistance dependent upon an applied pressure thereto; and a soft buffer structure formed around the PE material and PR material, the buffer structure disposed between the PE and PR materials and the stiffener structure, wherein the stiffener structure clamps both the PE and PR materials to a substrate over which the PE and PR materials are formed, and wherein the soft buffer structure permits the PE material freedom to move relative to the PR material, thereby coupling stress generated by an applied voltage to the PE material to the PR material so as change the electrical resistance of the PR material.

Abstract: A coupling structure for coupling piezoelectric material generated stresses to an actuated device of an integrated circuit includes a rigid stiffener structure formed around a piezoelectric (PE) material and the actuated device, the actuated device comprising a piezoresistive (PR) material that has an electrical resistance dependent upon an applied pressure thereto; and a soft buffer structure formed around the PE material and PR material, the buffer structure disposed between the PE and PR materials and the stiffener structure, wherein the stiffener structure clamps both the PE and PR materials to a substrate over which the PE and PR materials are formed, and wherein the soft buffer structure permits the PE material freedom to move relative to the PR material, thereby coupling stress generated by an applied voltage to the PE material to the PR material so as change the electrical resistance of the PR material.

Abstract: A memory cell device includes a semiconductor nanowire extending, at a first end thereof, from a substrate; the nanowire having a doping profile so as to define a field effect transistor (FET) adjacent the first end, the FET further including a gate electrode at least partially surrounding the nanowire, the doping profile further defining a p-n junction in series with the FET, the p-n junction adjacent a second end of the nanowire; and a phase change material at least partially surrounding the nanowire, at a location corresponding to the p-n junction.

Abstract: A coupling structure for coupling piezoelectric material generated stresses to an actuated device of an integrated circuit includes a rigid stiffener structure formed around a piezoelectric (PE) material and the actuated device, the actuated device comprising a piezoresistive (PR) material that has an electrical resistance dependent upon an applied pressure thereto; and a soft buffer structure formed around the PE material and PR material, the buffer structure disposed between the PE and PR materials and the stiffener structure, wherein the stiffener structure clamps both the PE and PR materials to a substrate over which the PE and PR materials are formed, and wherein the soft buffer structure permits the PE material freedom to move relative to the PR material, thereby coupling stress generated by an applied voltage to the PE material to the PR material so as change the electrical resistance of the PR material.

Abstract: Programmable via devices and methods for the fabrication thereof are provided. In one aspect, a programmable via device is provided.

Abstract: A memory cell device includes a semiconductor nanowire extending, at a first end thereof, from a substrate; the nanowire having a doping profile so as to define a field effect transistor (FET) adjacent the first end, the FET further including a gate electrode at least partially surrounding the nanowire, the doping profile further defining a p-n junction in series with the FET, the p-n junction adjacent a second end of the nanowire; and a phase change material at least partially surrounding the nanowire, at a location corresponding to the p-n junction.

Abstract: A switching circuit includes a plurality of three-terminal PCM switching devices connected between a voltage supply terminal and a sub-block of logic. Each of the switching devices includes a PCM disposed in contact between a first terminal and a second terminal, a heating device disposed in contact between the second terminal and a third terminal, the heating device positioned proximate the PCM, and configured to switch the conductivity of a transformable portion of the PCM between a lower resistance state and a higher resistance state; and an insulating layer configured to electrically isolate the heater from said PCM material, and the heater from the first terminal. The third terminal of a first of the PCM switching devices is coupled to a set/reset switch, and the third terminal of the remaining PCM switching devices is coupled to the second terminal of an adjacent PCM switching device in a cascade configuration.

Abstract: A piezo-effect transistor (PET) device includes a piezoelectric (PE) material disposed between first and second electrodes; and a piezoresistive (PR) material disposed between the second electrode and a third electrode, wherein the first electrode comprises a gate terminal, the second electrode comprises a common terminal, and the third electrode comprises an output terminal such that an electrical resistance of the PR material is dependent upon an applied voltage across the PE material by way of an applied pressure to the PR material by the PE material.

Abstract: A switching circuit includes a plurality of three-terminal PCM switching devices connected between a voltage supply terminal and a sub-block of logic. Each of the switching devices includes a PCM disposed in contact between a first terminal and a second terminal, a heating device disposed in contact between the second terminal and a third terminal, the heating device positioned proximate the PCM, and configured to switch the conductivity of a transformable portion of the PCM between a lower resistance state and a higher resistance state; and an insulating layer configured to electrically isolate the heater from said PCM material, and the heater from the first terminal. The third terminal of a first of the PCM switching devices is coupled to a set/reset switch, and the third terminal of the remaining PCM switching devices is coupled to the second terminal of an adjacent PCM switching device in a cascade configuration.

Abstract: Reconfigurable devices and methods for the fabrication thereof are provided. In one aspect, a reconfigurable device is provided.

Abstract: Programmable via devices and methods for the fabrication thereof are provided. In one aspect, a programmable via device is provided.

Abstract: Programmable via devices and methods for the fabrication thereof are provided. In one aspect, a programmable via device is provided.

Abstract: Programmable via devices and methods for the fabrication thereof are provided. In one aspect, a programmable via device is provided.

Abstract: A coupling structure for coupling piezoelectric material generated stresses to an actuated device of an integrated circuit includes a rigid stiffener structure formed around a piezoelectric (PE) material and the actuated device, the actuated device comprising a piezoresistive (PR) material that has an electrical resistance dependent upon an applied pressure thereto; and a soft buffer structure formed around the PE material and PR material, the buffer structure disposed between the PE and PR materials and the stiffener structure, wherein the stiffener structure clamps both the PE and PR materials to a substrate over which the PE and PR materials are formed, and wherein the soft buffer structure permits the PE material freedom to move relative to the PR material, thereby coupling stress generated by an applied voltage to the PE material to the PR material so as change the electrical resistance of the PR material.

Abstract: A memory cell device includes a semiconductor nanowire extending, at a first end thereof, from a substrate; the nanowire having a doping profile so as to define a field effect transistor (FET) adjacent the first end, the FET further including a gate electrode at least partially surrounding the nanowire, the doping profile further defining a p-n junction in series with the FET, the p-n junction adjacent a second end of the nanowire; and a phase change material at least partially surrounding the nanowire, at a location corresponding to the p-n junction.

Abstract: Reconfigurable devices and methods for the fabrication thereof are provided. In one aspect, a reconfigurable device is provided.

Abstract: A method of fabricating a programmable via structure is provided. The method includes providing a patterned heating material on a surface of an oxide layer. The oxide layer is located above a semiconductor substrate. A patterned dielectric material is formed having a least one via on a surface of the patterned heating material. The at least one via is filled with a phase change material such that a lower surface of the phase change material is in direct contact with a portion of the patterned heating material. A patterned diffusion barrier is formed on an exposed surface of the at least one via filled with the phase change material. A method of programmable a programmable via structure made by the method is also disclosed.