Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method further includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method further includes removing the first oxide layer using a H3PO4 solution.

Abstract: A package structure is provided. The package structure includes an encapsulant and an interposer. The encapsulant has a top surface and a bottom surface opposite to the top surface. The interposer is encapsulated by the encapsulant. The interposer includes a main body, an interconnector, and a stop layer. The main body has a first surface and a second surface opposite to the first surface. The interconnector is disposed on the first surface and exposed from the top surface of the encapsulant. The stop layer is on the second surface, wherein a bottom surface of the stop layer is lower than the second surface.

Abstract: In an embodiment of the disclosure, disclosed is a circuit based on in-memory computing in a digital domain, including: an array of computational storage cells, the computational storage cells including a preset number of data storage cells and a preset number of single-bit multipliers in one-to-one correspondence; an adder tree configured to accumulate products output by respective computational storage cells to obtain an accumulated result; and a multi-bit input transfer logic configured to convert accumulated results output by the adder tree and corresponding to respective single bits included in the input feature data into a multiply-accumulate result of multi-bit input feature data and multi-bit weight data. An in-memory multiply-accumulation is implemented or multi-bit weight data and input feature data, so that efficiency and energy efficiency density of in-memory computing is improved, “read disturb write” issue caused by a voltage change on bit lines is avoided, and computing stability is improved.

Abstract: A coupler for coupling an endoscope to a camera head includes a base configured to mount to the camera head and to receive an eyepiece of the endoscope; a clamp for clamping the eyepiece in the base, the clamp configured to move laterally relative to a longitudinal axis of the coupler between a clamping position and non-clamping position; at least one clamping arm rotatably connected to the clamp and comprising a pin that moves in a slot of the base, wherein when the clamp moves laterally toward the clamping position, movement of the pin in the slot causes the at least one clamping arm to rotate into engagement with the eyepiece; and a button for pressing by a user to move the clamp from the clamping position to the non-clamping position.

Abstract: A method of providing a visual indication that information is being saved or broadcast includes providing at least one recording device for obtaining the information, providing a system for saving and/or broadcasting the information obtained from the at least one recording device, providing at least one monitor for viewing the information, providing a plurality of visual indications, and activating the plurality of visual indications when the information is being saved or broadcast.

Abstract: A deflecting plate includes a silicon-on-insulator (SOI) substrate. The SOI substrate includes: an insulator layer having a top surface and a bottom surface; a device layer coupled to the insulator layer at the top surface, wherein multiple deflecting apertures are disposed in the device layer, each of which extending from a top open end to a bottom open end through the device layer, and wherein the bottom open end is coplanar with the top surface of the insulator layer; and a handle substrate coupled to the insulator layer at the bottom surface, wherein a cavity is disposed in the handle substrate and extends from a cavity open end to a cavity bottom wall, and wherein the bottom wall is coplanar with the top surface of the insulator layer, such that the bottom open end of each deflecting aperture is exposed to the cavity.

Abstract: A method of generating an IC layout diagram includes receiving an IC layout diagram including a gate region and a gate via, the gate via being positioned at a location within an active region and along a width of the gate region extending across the active region, receiving a first gate resistance value of the gate region, retrieving a second gate resistance value from a resistance value reference based on the location and the width, using the first and second resistance values to determine that the IC layout diagram does not comply with a design specification, and based on the non-compliance with the design specification, modifying the IC layout diagram.

Abstract: A method for forming a high electron mobility transistor is disclosed. A mesa structure having a channel layer and a barrier layer is formed on a substrate. The mesa structure has two first edges extending along a first direction and two second edges extending along a second direction. A passivation layer is formed on the substrate and the mesa structure. A first opening and a plurality of second openings connected to a bottom surface of the first opening are formed and through the passivation layer, the barrier layer and a portion of the channel layer. In a top view, the first opening exposes the two first edges of the mesa structure without exposing the two second edges of the mesa structure. A metal layer is formed in the first opening and the second openings thereby forming a contact structure.

Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a stopping assembly. The fixed assembly has a main axis. The movable assembly is configured to connect an optical element, and the movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The stopping assembly is configured to limit the movement of the movable assembly relative to the fixed assembly within a range of motion.

Abstract: The present disclosure provides a fracturing device driven by a variable-frequency adjustable-speed integrated machine (VFASIM), including the VFASIM and a plunger pump. The VFASIM includes a driving device for providing a driving force and an inverting device integrally installed on the driving device. The inverting device supplies power to the driving device. The plunger pump is integrally installed together with the VFASIM, the plunger pump is mechanically connected to the driving device of the VFASIM and driven by the driving device. According to the present disclosure, it is possible to achieve an overall layout with a high degree of integration. The present disclosure also provides a well site layout including a plurality of fracturing devices described above.

Abstract: A semiconductor device with different configurations of gate structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a gate opening on the fin structure, forming a metallic oxide layer within the gate opening, forming a first dielectric layer on the metallic oxide layer, forming a second dielectric layer on the first dielectric layer, forming a work function metal (WFM) layer on the second dielectric layer, and forming a gate metal fill layer on the WFM layer. The forming the first dielectric layer includes depositing an oxide material with an oxygen areal density less than an oxygen areal density of the metallic oxide layer.

Abstract: An operation-indication mode switching structure, a circuit, and a method for operating the same are provided. The operation-indication mode switching structure is disposed on a housing of a device, and includes a switching mechanism that is used to switch multiple operation-indication modes. The switching mechanism is selectively connected with one of multiple signal terminals. When the switching mechanism is manipulated to switch to one of the operation-indication modes, a control unit of the device receives an operation-indication mode switching signal generated by the switching mechanism conducting or circuit-shorting one of the multiple signal terminals. A corresponding operation-indication mode that is a covert mode, a stealth mode, or a normal mode can be determined. The control unit is used to control an indication function of the device according to the operation-indication mode that is switched to.

Abstract: A body-worn camera and an operation method thereof are provided, and the body-worn camera a central processing unit, a video recording module, a turntable, and a main button. The video recording module is electrically connected to the central processing unit. The turntable is electrically connected to the central processing unit. The main button is electrically connected to the central processing unit. After the video recording module completes recording a video, when the central processing unit receives a category mode signal from the turntable and receives a category name confirmation signal from the main button, the central processing unit executes a video tagging program, and the video tagging program saves a corresponding relationship between a category name and the video.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first source/drain epitaxial feature formed over a substrate, a second source/drain epitaxial feature formed over the substrate, two or more semiconductor layers disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature, a gate electrode layer surrounding a portion of one of the two or more semiconductor layers, a first dielectric region disposed in the substrate and in contact with a first side of the first source/drain epitaxial feature, and a second dielectric region disposed in the substrate and in contact with a first side of the second source/drain epitaxial feature, the second dielectric region being separated from the first dielectric region by a substrate.

Abstract: In an embodiment, a method includes: placing a wafer on an implanter platen, the wafer including alignment marks; measuring a position of the wafer by measuring positions of the alignment marks with one or more cameras; determining an angular displacement between the position of the wafer and a reference position of the wafer; and rotating the implanter platen by the angular displacement.

Abstract: A device includes a fin extending from a semiconductor substrate; a gate stack over the fin; a first spacer on a sidewall of the gate stack; a source/drain region in the fin adjacent the first spacer; an inter-layer dielectric layer (ILD) extending over the gate stack, the first spacer, and the source/drain region, the ILD having a first portion and a second portion, wherein the second portion of the ILD is closer to the gate stack than the first portion of the ILD; a contact plug extending through the ILD and contacting the source/drain region; a second spacer on a sidewall of the contact plug; and an air gap between the first spacer and the second spacer, wherein the first portion of the ILD extends across the air gap and physically contacts the second spacer, wherein the first portion of the ILD seals the air gap.

Abstract: A carrier structure is provided, in which at least one positioning area is defined on a chip-placement area of a package substrate, and at least one alignment portion is disposed on the positioning area. Therefore, the precision of manufacturing the alignment portion is improved by disposing the positioning area on the chip-placement area, such that the carrier structure can provide a better alignment mechanism for the chip placement operation.

Abstract: The present invention discloses an organic polymer film and a manufacturing method thereof. The organic polymer film is mainly manufactured by the following steps. Firstly, the step (A) provides a xylene precursor and a substrate, and the step (B) places the substrate inside of a plasma equipment. After that, the step (C) evacuates the plasma equipment while introducing a carrier gas which carries vapor of the xylene precursor, and the step (D) turns on a pulse power supply system of the plasma equipment, generating a short pulse for plasma ignition. Finally, the step (E) forms the organic polymer film on the substrate. In the aforementioned steps, the frequency of the short pulse plasma is between 1 Hz˜10,000 Hz, and the pulse period of the short pulse plasma is between 1 ?s˜60 ?s.

Abstract: A semiconductor structure includes a substrate and a first capacitor. The substrate includes an active region. The first capacitor is over the substrate and free from overlapping the active region from a top view perspective.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes an interconnect structure overlying a semiconductor substrate and comprising a conductive wire. A passivation structure overlies the interconnect structure. An upper conductive structure overlies the passivation structure and comprises a first conductive layer, a dielectric layer, and a second conductive layer. The first conductive layer is disposed between the dielectric layer and the passivation structure. The second conductive layer extends along a top surface of the dielectric layer and penetrates through the first conductive layer and the passivation structure to the conductive wire.