Abstract: Innovative techniques to design and generate haptics waveforms are proposed. The proposed techniques reduce or eliminate audible noises being generated by a haptic actuator during operation. A haptic controller may compose a voltage waveform at a resonant frequency of the haptic actuator and generate a corresponding control signal. Instead of suddenly entering a high impedance state from a driving state, the voltage waveform may include a ramp down portion in which the voltage ramps down continuously but quickly so that the current flowing within the actuator is brought down before entering the high impedance state. In this way, audible noises may be reduced or even eliminated.

Abstract: Innovative techniques to design and generate haptics waveforms are proposed. The proposed techniques reduce or eliminate audible noises being generated by a haptic actuator during operation. A haptic controller may compose a voltage waveform at a resonant frequency of the haptic actuator and generate a corresponding control signal. Instead of suddenly entering a high impedance state from a driving state, the voltage waveform may include a ramp down portion in which the voltage ramps down continuously but quickly so that the current flowing within the actuator is brought down before entering the high impedance state. In this way, audible noises may be reduced or even eliminated.

Abstract: In some implementations, a measurement circuit may drive, using a first transistor, a first node of a haptic load. The measurement circuit may trigger a first comparator when a voltage driving the haptic load satisfies a first condition. The first comparator may have a first node connected, in parallel, to a drain of a second transistor and may have a second node connected to the first node of the haptic load. Additionally, the second transistor may have a gate connected to a gate of the first transistor and may have the drain connected to a first reference current.

Abstract: Certain aspects are directed to a circuit for brightness control. The circuit generally includes: a duty cycle adjustment circuit configured to receive a first backlight control signal having a first duty cycle and generate a second backlight control signal having a second duty cycle, the second duty cycle being greater than the first duty cycle if the first duty cycle is less than a threshold; a digital processor configured to set a value of a software brightness code based on the second duty cycle; and a backlight control circuit configured to drive a backlight in accordance with the software brightness code and the second duty cycle of the second backlight control signal.

Abstract: In some implementations, a measurement circuit may drive, using a first transistor, a first node of a haptic load. The measurement circuit may trigger a first comparator when a voltage driving the haptic load satisfies a first condition. The first comparator may have a first node connected, in parallel, to a drain of a second transistor and may have a second node connected to the first node of the haptic load. Additionally, the second transistor may have a gate connected to a gate of the first transistor and may have the drain connected to a first reference current.

Abstract: Certain aspects are directed to a circuit for brightness control. The circuit generally includes: a duty cycle adjustment circuit configured to receive a first backlight control signal having a first duty cycle and generate a second backlight control signal having a second duty cycle, the second duty cycle being greater than the first duty cycle if the first duty cycle is less than a threshold; a digital processor configured to set a value of a software brightness code based on the second duty cycle; and a backlight control circuit configured to drive a backlight in accordance with the software brightness code and the second duty cycle of the second backlight control signal.

Abstract: A low drop-out regulator circuit comprises a pass transistor providing an output voltage on an output terminal in response to a gate voltage on a gate of the pass transistor. A feedback circuit is coupled to the output terminal to generate a feedback voltage, and an error amplifier provides a drive signal in response to a reference voltage and the feedback voltage. A first gate driver circuit is operable over a first voltage range to provide the gate voltage to the pass transistor in response to the drive signal. A second gate driver circuit is operable over a second voltage range to provide the gate voltage to the pass transistor in response to the drive signal, where the second voltage range is lower than the first voltage range.

Abstract: In one embodiment, the present disclosure includes a low drop-out regulator circuit comprising a pass transistor providing an output voltage on an output terminal in response to a gate voltage on a gate of the pass transistor. A feedback circuit is coupled to the output terminal to generate a feedback voltage, and an error amplifier provides a drive signal in response to a reference voltage and the feedback voltage. A first gate driver circuit is operable over a first voltage range to provide the gate voltage to the pass transistor in response to the drive signal. A second gate driver circuit is operable over a second voltage range to provide the gate voltage to the pass transistor in response to the drive signal, where the second voltage range is lower than the first voltage range.

Abstract: In one embodiment, a low-dropout regulator comprises a pass transistor having a first terminal to receive an input voltage, a second terminal to provide an output voltage, and a gate terminal. A feedback circuit is coupled between the second terminal of the pass transistor and ground to generate a feedback voltage in response to the output voltage. A comparator has an output to generate a control voltage in response to the feedback voltage and a reference voltage. A switch is coupled between the output of the charge pump and the gate terminal of the pass transistor to selectively provide the control voltage to the gate terminal.

Abstract: Embodiments described herein relate to an improved circuit technique in a rail-to-rail input stage circuit utilizing non-complementary differential pairs with bias control designed to maintain a constant transconductance “gm” throughout an input common mode voltage range. The rail-to-rail input stage circuit comprises a first differential pair circuit, a level-shifted differential pair circuit coupled with the first differential pair circuit, and a constant transconductance generation circuit coupled with the level-shifted differential pair circuit. The constant transconductance generation circuit is configured to control the bias current conducting in the level-shifted differential pair circuit based on current conducting in the first differential pair circuit to maintain a constant transconductance in the rail-to-rail input stage circuit.

Abstract: In one embodiment, a low-dropout regulator comprises a pass transistor having a first terminal to receive an input voltage, a second terminal to provide an output voltage, and a gate terminal. A feedback circuit is coupled between the second terminal of the pass transistor and ground to generate a feedback voltage in response to the output voltage. A comparator has an output to generate a control voltage in response to the feedback voltage and a reference voltage. A switch is coupled between the output of the charge pump and the gate terminal of the pass transistor to selectively provide the control voltage to the gate terminal.

Abstract: In one embodiment, a circuit includes a first transistor having a control terminal, a first terminal, and a second terminal where the first transistor is a first device type. The control terminal of the first transistor receives an input signal. The circuit also includes a second transistor having a control terminal, a first terminal, and a second terminal where the second transistor is a second device type. The control terminal of the second transistor is coupled to the second terminal of the first transistor. A voltage shift circuit has an input coupled to the first terminal of the first transistor and an output coupled to the first terminal of the second transistor and a voltage between the input of the voltage shift circuit and an output of the voltage shift circuit increases as a current from the output of the voltage shift circuit increases.

Abstract: In one embodiment, a circuit includes a first transistor having a control terminal, a first terminal, and a second terminal where the first transistor is a first device type. The control terminal of the first transistor receives an input signal. The circuit also includes a second transistor having a control terminal, a first terminal, and a second terminal where the second transistor is a second device type. The control terminal of the second transistor is coupled to the second terminal of the first transistor. A voltage shift circuit has an input coupled to the first terminal of the first transistor and an output coupled to the first terminal of the second transistor and a voltage between the input of the voltage shift circuit and an output of the voltage shift circuit increases as a current from the output of the voltage shift circuit increases.

Abstract: One feature pertains to a method that includes implementing a Physical Unclonable Function (PUF) circuit, and obtaining a first set of output bits from the PUF circuit by operating the PUF circuit at a first supply voltage level and/or first frequency. Then, at least one of the first supply voltage level is changed to a second supply voltage level and/or the first frequency is changed to a second frequency, where the second supply voltage level and the second frequency are different than the first supply voltage level and the first frequency, respectively. A second set of output bits is then obtained by operating the PUF circuit at the second supply voltage level and/or the second frequency, where the second set of output bits is in part different than the first set. Secure data is generated using the first set of output bits and the second sets of output bits.

Abstract: One feature pertains to a method that includes implementing a Physical Unclonable Function (PUF) circuit, and obtaining a first set of output bits from the PUF circuit by operating the PUF circuit at a first supply voltage level and/or first frequency. Then, at least one of the first supply voltage level is changed to a second supply voltage level and/or the first frequency is changed to a second frequency, where the second supply voltage level and the second frequency are different than the first supply voltage level and the first frequency, respectively. A second set of output bits is then obtained by operating the PUF circuit at the second supply voltage level and/or the second frequency, where the second set of output bits is in part different than the first set. Secure data is generated using the first set of output bits and the second sets of output bits.