Abstract: A method for detecting an abnormal die includes providing a wafer, determining the surrounding dies in accordance with a position of a target die on the wafer, calculating a difference between a value of an electrical characteristic of each of the surrounding dies and a value of an electrical characteristic of the target die to obtain the electrical characteristic deviations, ranking the absolute values of the electrical characteristic deviations to generate a ranking result, and determining the characteristic-related dies from the surrounding dies in accordance with the ranking result, determining a target-related area in accordance with the position of the target die, determining the target-related die from the characteristic-related dies in accordance with the target-related area and determining whether the target die is qualified in accordance with the target-related die.

Abstract: A memory inspecting method and a memory inspecting system are proposed. The memory inspecting system includes a testing machine and a computer system. The memory inspecting method includes: performing a first data retention time test on a plurality of memory chips to obtain a plurality of first qualified memory chips; performing a second data retention time test on the first qualified memory chips to obtain a plurality of second qualified memory chips; performing a third data retention time test on the second qualified memory chips to obtain a plurality of third qualified memory chips. Performing a statistical analysis step on the third qualified memory chips according to a first data retention time, a second data retention time and a third data retention time of each of the third qualified memory chips is for obtaining at least one final qualified memory chip.

Abstract: A method for detecting an abnormal die includes providing a wafer, determining the surrounding dies in accordance with a position of a target die on the wafer, calculating a difference between a value of an electrical characteristic of each of the surrounding dies and a value of an electrical characteristic of the target die to obtain the electrical characteristic deviations, ranking the absolute values of the electrical characteristic deviations to generate a ranking result, and determining the characteristic-related dies from the surrounding dies in accordance with the ranking result, determining a target-related area in accordance with the position of the target die, determining the target-related die from the characteristic-related dies in accordance with the target-related area and determining whether the target die is qualified in accordance with the target-related die.

Abstract: A memory inspecting method and a memory inspecting system are proposed. The memory inspecting system includes a testing machine and a computer system. The memory inspecting method includes: performing a first data retention time test on a plurality of memory chips to obtain a plurality of first qualified memory chips; performing a second data retention time test on the first qualified memory chips to obtain a plurality of second qualified memory chips; performing a third data retention time test on the second qualified memory chips to obtain a plurality of third qualified memory chips. Performing a statistical analysis step on the third qualified memory chips according to a first data retention time, a second data retention time and a third data retention time of each of the third qualified memory chips is for obtaining at least one final qualified memory chip.

Abstract: A device for detecting defective memory includes a first global word line; a second global word line; a global word-line front end, connected to the first global word line; a global word-line driver, connected to the global word-line front end and driving the first global word line; a local word-line driver, connected to the first global word line and driving a local word line; and a voltage-controlled transistor, including a first terminal connected to the first global word line, a second terminal connected to a connection line between the global word-line front end and the global word-line driver, and a third terminal outputting a test current.

Abstract: By inputting voltages to global word lines of a memory, and by detecting currents of corresponding global word lines, a relation function between the currents and the voltages can be generated, and connection defects on the global word lines can be determined according to various types of deviation of a relation curve corresponding to the relation function between the currents and voltages.

Abstract: Utilize a pattern generator to write a predetermined logic voltage to each memory cell of a memory chip. Read a predetermined logic voltage stored in the memory cell. Compare the predetermined logic voltage stored in the memory cell with the predetermined logic voltage to determine if the memory cell is a good memory cell or not and store a determination result corresponding to the memory cell in a data latch of the memory chip. And determine if the memory chip is a good memory chip or not according to determination results of all memory cells of the memory chip stored in the data latch of the memory chip.

Abstract: By inputting voltages to global word lines of a memory, and by detecting currents of corresponding global word lines, a relation function between the currents and the voltages can be generated, and connection defects on the global word lines can be determined according to various types of deviation of a relation curve corresponding to the relation function between the currents and voltages.

Abstract: A connector applied to a portable device includes a wireless module, a connection module, at least one connection socket, a controller, and a memory. The wireless module is used for establishing a wireless connection between the portable device and the connector. The connection module is used for communicating with an external device. The at least one connection socket is used for connecting the connection module with the external device. The controller is coupled between the wireless module and the connection module for transmitting data between the wireless module and the connection module and executing commands to control the wireless module and the connection module. The memory is used for storing the commands required for the controller and is used as a data register to boost a data transmission rate between the portable device and the external device.

Abstract: Utilize a pattern generator to write a predetermined logic voltage to each memory cell of a memory chip. Read a predetermined logic voltage stored in the memory cell. Compare the predetermined logic voltage stored in the memory cell with the predetermined logic voltage to determine if the memory cell is a good memory cell or not and store a determination result corresponding to the memory cell in a data latch of the memory chip. And determine if the memory chip is a good memory chip or not according to determination results of all memory cells of the memory chip stored in the data latch of the memory chip.

Abstract: Method for detecting word line defect includes activating a first word line for reading a first data pre-stored in the memory cell, suspending the first word line for a predetermined period and then writing a second data complementary to the first data into the memory cell, activating again the first word line for reading a third data from the memory cell, and comparing the second and the third data for determining if an electrical coupling path exists between the first word line and a second word line.

Abstract: Method for detecting word line defect includes activating a first word line for reading a first data pre-stored in the memory cell, suspending the first word line for a predetermined period and then writing a second data complementary to the first data into the memory cell, activating again the first word line for reading a third data from the memory cell, and comparing the second and the third data for determining if an electrical coupling path exists between the first word line and a second word line.

Abstract: A method detects if a word line of a memory array is broken. The method includes writing a first datum to a memory cell when coupling a corresponding word line to a voltage source, writing a second datum different from the first datum to the memory cell when the coupling between the corresponding word line and the voltage source is decoupled, reading the stored data of the memory cell, and determining if the word line is broken according to the read data, the first datum, and the second datum.

Abstract: A method detects if a word line of a memory array is broken. The method includes writing a first datum to a memory cell when coupling a corresponding word line to a voltage source, writing a second datum different from the first datum to the memory cell when the coupling between the corresponding word line and the voltage source is decoupled, reading the stored data of the memory cell, and determining if the word line is broken according to the read data, the first datum, and the second datum.