Abstract: A central processing unit (CPU) includes a plurality of physical registers and instruction queues; a respective queue respectively configured to buffer instructions for execution; the instructions referencing one or more of the physical registers. The CPU includes a dispatching circuitry configured to: i) when a respective instruction is an independent load instruction, which is a load instruction to load data from an addressable memory into a physical register, and is independent from instructions buffered in the instruction queues through the physical registers, then dispatch the respective instruction to a first queue of the instruction queues; and ii) when the respective instruction is a dependent instruction dependent on the independent load instruction, then dispatch the respective instruction to another queue of the instruction queues.

Abstract: A method for simulating a set of instructions to be executed on a processor including performing a performance simulation of the processor over a number of simulation cycles. Modeling, in a frontend component, branch prediction and instruction cache is performed providing instructions to the instruction window, and modeling of an instruction window for the cycle is performed. From the simulation, a performance parameter of the processor is obtained without modeling a reorder buffer, issue queue(s), register renaming, load-store queue(s) and other buffers of the processor.

Abstract: A method and system are described for simulating a set of instructions to be executed on a processor. The method comprises performing a performance simulation of the processor over a number of simulation cycles. Performing the performance simulation of the processor comprises modeling an instruction window for the cycle and deriving a performance parameter of the processor without modeling a reorder buffer, issue queue(s), register renaming, load-store queue(s) and other buffers of the processor.

Abstract: A counter architecture and a corresponding method are provided for estimating a profitability value of DVFS for a unit of work running on a computing device. The counter architecture and the corresponding method are arranged for dividing total execution time for executing a unit of work on the computing device into a pipelined fraction subject to clock frequency and a non-pipelined fraction due to off-chip memory accesses, and for estimating the DVFS profitability value from the pipelined and the non-pipelined fraction.

Abstract: A counter architecture and a corresponding method are provided for estimating a profitability value of DVFS for a unit of work running on a computing device. The counter architecture and the corresponding method are arranged for dividing total execution time for executing a unit of work on the computing device into a pipelined fraction subject to clock frequency and a non-pipelined fraction due to off-chip memory accesses, and for estimating the DVFS profitability value from the pipelined and the non-pipelined fraction.

Abstract: A method is described for simulating a set of instructions to be executed on a processor. The method comprises performing a functional simulation of the processor over a number of simulation cycles. Performing the functional simulation of the processor thereby may comprise using an analytical model comprising a timing estimator and estimating during the functional simulation timing information of the processor.