Abstract: An electronic device includes a first-conductivity-type substrate and a second-conductivity-type epitaxial layer having a first dopant concentration. A first substrate region includes a second-conductivity-type buried layer and is enclosed by a first deep isolation structure. Within the first substrate region are a first doped region having the second conductivity type and a dopant concentration greater than the first dopant concentration and a second doped region having the first conductivity type. A second substrate region includes a first-conductivity-type buried layer and is enclosed by a second deep isolation structure. Within the second substrate region is a third doped region having the second conductivity type and a dopant concentration greater than the first dopant concentration.

Abstract: An electronic device includes a first-conductivity-type substrate and a second-conductivity-type epitaxial layer having a first dopant concentration. A first substrate region includes a second-conductivity-type buried layer and is enclosed by a first deep isolation structure. Within the first substrate region are a first doped region having the second conductivity type and a dopant concentration greater than the first dopant concentration and a second doped region having the first conductivity type. A second substrate region includes a first-conductivity-type buried layer and is enclosed by a second deep isolation structure. Within the second substrate region is a third doped region having the second conductivity type and a dopant concentration greater than the first dopant concentration.

Abstract: A protective SCR integrated circuit device is disclosed built on adjacent N and P wells and defining an anode and a cathode. In addition to the anode and cathode contact structures, the device has an n-type stack (N+/ESD) structure bridging the N-Well and the P-Well, and a p-type stack (P+/PLDD) structure in the P-Well. The separation of the n-type stack structure and the p-type stack structure provides a low triggering voltage without involving any external circuitry or terminal, that together with other physical dimensions and processing parameters also provide a relatively high holding voltage without sacrificing the ESD protection robustness. In an embodiment, the triggering voltage may be about 8V while exhibiting a holding voltage, that may be controlled by the lateral dimension of the n-type stack of about 5-7 V.

Abstract: A protective SCR integrated circuit device is disclosed built on adjacent N and P wells and defining an anode and a cathode. In addition to the anode and cathode contact structures, the device has an n-type stack (N+/ESD) structure bridging the N-Well and the P-Well, and a p-type stack (P+/PLDD) structure in the P-Well. The separation of the n-type stack structure and the p-type stack structure provides a low triggering voltage, that together with other physical dimensions and processing parameters also provide a relatively high holding voltage. In an embodiment, the triggering voltage may be about 8V while exhibiting a holding voltage, that may be controlled by the lateral dimension of the n-type stack of about 5-7 V.