Abstract: A method, apparatus and program storage device for managing dataflow through a processing system is disclosed. A buffer monitor maintains and monitors a buffer full threshold to control the write throughput to a data bus.

Abstract: An apparatus, system, and method are disclosed for the recovery from a design defect in an integrated circuit. The apparatus includes an error check module, a control settings module, a retry module, and a recovery module. The error check module discovers that an error has occurred during an operation. The control settings module changes the contents of one or more system control registers according to a set of system control settings that change the logic path of one or more system signals. The retry module executes the operation. The recovery module discovers that the operation was executed successfully.

Abstract: A method, apparatus and program storage device for managing dataflow through a processing system is disclosed. A buffer monitor maintains and monitors a buffer full threshold to control the write throughput to a data bus.

Abstract: An apparatus, system, and method are provided for managing errors in prefetched data. The apparatus, system, and method identify prefetched data that contains an uncorrectable error. In addition, the apparatus, system, and method initiate an error recovery process only for prefetched data that is actually used by a requesting device, module, or application. The apparatus includes a prefetch module that prefetches data packets, a validation module that determines whether a prefetched data packet contains an uncorrectable error, a transfer module that transfers prefetched data packets to a requester, and an error recovery module that selectively initiates error recovery for those data packets that contain an uncorrectable error and are actually transferred to the requester.

Abstract: The present invention relates to a method for the real-time detection and prevention or correction of errors within an IC environment. The method comprises the steps of determining an event, or a sequence of events set, wherein these event set serve as triggers for a defect event within an IC, and configuring a logic analyzer that is embedded within the IC to monitor the operations of the IC in order to detect occurrences of defect event triggers within the IC. Further, the IC defect event trigger information is transmitted from the embedded logic analyzer to an IC hardware sequencer, wherein the hardware sequencer is configured to initiate actions to correct the defect event.

Abstract: A method, apparatus and program storage device for managing dataflow through a processing system is disclosed. A buffer monitor maintains and monitors a buffer full threshold to control the write throughput to a data bus.

Abstract: An apparatus, system, and method are disclosed for the recovery from a design defect in an integrated circuit. The apparatus includes an error check module, a control settings module, a retry module, and a recovery module. The error check module discovers that an error has occurred during an operation. The control settings module changes the contents of one or more system control registers according to a set of system control settings that change the logic path of one or more system signals. The retry module executes the operation. The recovery module discovers that the operation was executed successfully.

Abstract: A device, system and method of data compression are provided. The invention includes a receiving module that may be a memory module. The invention also includes a pointer module storing a pointer to a location within the receiving module. The invention allocates a receiving space within the receiving module and associates the pointer with the receiving space. The pointer may be associated with the beginning of the receiving space. The invention compresses a first data block and directs the compressed first data block to the receiving space at the location indicated by the pointer. The invention further associates the pointer with the location in the receiving space contiguous with the received compressed first data block. The invention compresses a second data block and directs the compressed second data block to the location within the receiving space indicated by the pointer. The invention compresses data as contiguous compressed data blocks.

Abstract: An apparatus, system, and computer readable medium are disclosed for reducing data transmission overhead. The present invention teaches a data transmission device having a fragment receiving module that receives at least one data fragment corresponding to a data segment and a memory controller that stores the at least one data fragment within a data segment memory. The memory controller includes a data count register that tracks an accumulated data count for the data segment. If the accumulated data count attains a selected value, the memory controller forwards the data segment. In certain embodiments, the memory controller orders the data fragments within the segment memory according to a selected order. In certain embodiments, the data segment memory is capable of storing a plurality of data segments.

Abstract: A method, apparatus and program storage device for automatically presenting status from a host bus adapter until an error is detected is provided. Data is transmitted between the host bus adapter and a host. The host performs data transmission validation and determines whether data transmission was successful. The host bus adapter automatically sends status information when data transmission was successful, else the host bus adapter waits for status type identification from the host for transmission of data.

Abstract: An adapter card employs a multi-formatting execution unit, one or more descriptor queues and one or more communication channels. The multi-formatting execution unit formats each data transfer between two or more network devices based on one of a plurality of data formatting schemes with each data formatting scheme being at least partially dissimilar from the other data formatting schemes. The descriptor queue(s) store one or more job descriptors with each job descriptor being indicative of a selection of one of the data formatting schemes for formatting a corresponding data transfer between the network devices. The communication channels operable to selectively connect the descriptor queue(s) to the multi-formatting execution unit to facilitate an electrical communication of each one job descriptor from the descriptor queue(s) to the multi-formatting execution unit.

Abstract: A device, system and method of data compression are provided. The invention includes a receiving module that may be a memory module. The invention also includes a pointer module storing a pointer to a location within the receiving module. The invention allocates a receiving space within the receiving module and associates the pointer with the receiving space. The pointer may be associated with the beginning of the receiving space. The invention compresses a first data block and directs the compressed first data block to the receiving space at the location indicated by the pointer. The invention further associates the pointer with the location in the receiving space contiguous with the received compressed first data block. The invention compresses a second data block and directs the compressed second data block to the location within the receiving space indicated by the pointer. The invention compresses data as contiguous compressed data blocks.

Abstract: A method, apparatus and program storage device for managing dataflow through a processing system is disclosed. A buffer monitor maintains and monitors a buffer full threshold to control the write throughput to a data bus.

Abstract: An apparatus, system, and method are provided for managing errors in prefetched data. The apparatus, system, and method identify prefetched data that contains an uncorrectable error. In addition, the apparatus, system, and method initiate an error recovery process only for prefetched data that is actually used by a requesting device, module, or application. The apparatus includes a prefetch module that prefetches data packets, a validation module that determines whether a prefetched data packet contains an uncorrectable error, a transfer module that transfers prefetched data packets to a requester, and an error recovery module that selectively initiates error recovery for those data packets that contain an uncorrectable error and are actually transferred to the requester.

Abstract: A method, apparatus and program storage device for automatically presenting status from a host bus adapter until an error is detected is provided. Data is transmitted between the host bus adapter and a host. The host performs data transmission validation and determines whether data transmission was successful. The host bus adapter automatically sends status information when data transmission was successful, else the host bus adapter waits for status type identification from the host for transmission of data.

Abstract: A method, apparatus and program storage device for providing data integrity using check data and other metadata on a formatted storage medium.

Abstract: The present invention concerns a method, apparatus, and article of manufacture which provides an efficient way to change the function of a programmable logic unit included in a control device--where the control device manages the operational characteristics of a hardware unit--without having to disable system access to the hardware unit during the updating process. The hardware unit remains fully functional throughout execution of the updating method. To perform the update, the hardware unit must be connected to a host system by at least two communication channels. Each communication channel includes a control device including a programmable logic unit. The programmable logic unit is pre-programmed by a first data set which establishes its predetermined operational characteristics. Upgrading the programmable logic unit is accomplished by logically removing one of the communication channels leading from the host system to the hardware unit.