Patents by Inventor Lih-Juann Chen
Lih-Juann Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7498224Abstract: A method for growing strained Si layer and relaxed SiGe layer with multiple Ge quantum dots (QDs) on a substrate is disclosed. The method can reduce threading dislocation density, decrease surface roughness of the strained silicon and further shorten growth time for forming epitaxy layers than conventional method. The method includes steps of: providing a silicon substrate, forming a multiple Ge QDs layers; forming a layer of relaxed SixGe1-x; and forming a strained silicon layer in subsequence; wherein x is greater than 0 and less than 1.Type: GrantFiled: July 20, 2006Date of Patent: March 3, 2009Assignee: Industrial Technology Research InstituteInventors: Pang-Shiu Chen, Sheng-Wei Lee, Lih-Juann Chen, Chee-Wee Liu
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Patent number: 7202512Abstract: A construction of thin strain-relaxed SiGe layers and method for fabricating the same is provided. The construction includes a semiconductor substrate, a SiGe buffer layer formed on the semiconductor substrate, a Si(C) layer formed on the SiGe buffer layer, and an relaxed SiGe epitaxial layer formed on the Si(C) layer. The Si(C) layer is employed to change the strain-relaxed mechanism of the relaxed SiGe epitaxial layer formed on the Si(C) layer. Therefore, a thin relaxed SiGe epitaxial layer with low threading dislocation density, smooth surface is available. The fabricating time for fabricating the strain-relaxed SiGe layers is greatly reduced and the surface roughness is also improved.Type: GrantFiled: August 11, 2004Date of Patent: April 10, 2007Assignee: Industrial Technology Research InstituteInventors: Pang-Shiu Chen, Sheng-Wei Lee, Kao-Feng Liao, Lih-Juann Chen, Chee-Wee Liu
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Publication number: 20060255331Abstract: A method for growing strained Si layer and relaxed SiGe layer with multiple Ge quantum dots (QDs) on a substrate is disclosed. The method can reduce threading dislocation density, decrease surface roughness of the strained silicon and further shorten growth time for forming epitaxy layers than conventional method. The method includes steps of: providing a silicon substrate, forming a multiple Ge QDs layers; forming a layer of relaxed SixGe1-x; and forming a strained silicon layer in subsequence; wherein x is greater than 0 and less than 1.Type: ApplicationFiled: July 20, 2006Publication date: November 16, 2006Applicant: Industrial Technology Research InstituteInventors: Pang-Shiu Chen, Sheng-Wei Lee, Lih-Juann Chen, Chee-Wee Liu
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Patent number: 7102153Abstract: A method for growing strained Si layer and relaxed SiGe layer with multiple Ge quantum dots (QDs) on a substrate is disclosed. The method can reduce threading dislocation density, decrease surface roughness of the strained silicon and further shorten growth time for forming epitaxy layers than conventional method. The method includes steps of: providing a silicon substrate, forming a multiple Ge QDs layers; forming a layer of relaxed SixGe1-x; and forming a strained silicon layer in subsequence; wherein x is greater than 0 and less than 1.Type: GrantFiled: August 17, 2004Date of Patent: September 5, 2006Assignee: Industrial Technology Research InstituteInventors: Pang-Shiu Chen, Sheng-Wei Lee, Lih-Juann Chen, Chee-Wee Liu
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Publication number: 20050179028Abstract: A construction of thin strain-relaxed SiGe layers and method for fabricating the same is provided. The construction includes a semiconductor substrate, a SiGe buffer layer formed on the semiconductor substrate, a Si(C) layer formed on the SiGe buffer layer, and an relaxed SiGe epitaxial layer formed on the Si(C) layer. The Si(C) layer is employed to change the strain-relaxed mechanism of the relaxed SiGe epitaxial layer formed on the Si(C) layer. Therefore, a thin relaxed SiGe epitaxial layer with low threading dislocation density, smooth surface is available. The fabricating time for fabricating the strain-relaxed SiGe layers is greatly reduced and the surface roughness is also improved.Type: ApplicationFiled: August 11, 2004Publication date: August 18, 2005Inventors: Pang-Shiu Chen, Sheng-Wei Lee, Kao-Feng Liao, Lih-Juann Chen, Chee-Wee Liu
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Publication number: 20050045870Abstract: A method for growing strained Si layer and relaxed SiGe layer with multiple Ge quantum dots (QDs) on a substrate is disclosed. The method can reduce threading dislocation density, decrease surface roughness of the strained silicon and further shorten growth time for forming epitaxy layers than conventional method. The method includes steps of: providing a silicon substrate, forming a multiple Ge QDs layers; forming a layer of relaxed SixGe1-x; and forming a strained silicon layer in subsequence; wherein x is greater than 0 and less than 1.Type: ApplicationFiled: August 17, 2004Publication date: March 3, 2005Applicant: Industrial Technology Research InstituteInventors: Pang Chen, Sheng-Wei Lee, Lih-Juann Chen, Chee-Wee Liu
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Patent number: 6858123Abstract: The invention relates to a novel galvanizing solution for the galvanic deposition of copper. Hydroxylamine sulfate or hydroxylamine hydrochloride are utilized as addition reagents and added to the galvanizing solution during the galvanic deposition of copper which is used in the manufacture of semiconductors.Type: GrantFiled: August 25, 2000Date of Patent: February 22, 2005Assignee: Merck Patent Gesellschaft MIT Beschrankter HaftungInventors: Jung-Chih Hu, Wu-Chun Gau, Ting-Chang Chang, Ming-Shiann Feng, Chun-Lin Cheng, You-Shin Lin, Ying-Hao Li, Lih-Juann Chen
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Publication number: 20030045038Abstract: A method of forming a low-temperature polysilicon, comprising steps of: providing a substrate with a surface on which a buffer layer, an amorphous silicon layer and a metal silicide layer are sequentially formed; forming a plurality of metal pads on predetermined regions of the metal silicide layer; and providing a current on the metal pads to transform the amorphous silicon layer into a polysilicon layer.Type: ApplicationFiled: October 29, 2001Publication date: March 6, 2003Inventors: Hsin-Hsien Lin, Jam-Wem Lee, Shao-Liang Cheng, Lih-Juann Chen, Yuan-Ching Peng, Wen-Tung Wang
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Patent number: 6417118Abstract: A method for improving the moisture absorption of porous low dielectric film in an interconnect structure is disclosed. The porous low-k dielectric layer such as porous hydrosilsesquioxane (porous HSQ) or porous methyl silsesquioxane (porous MSQ) is spun-on the etching stop layer. After plasma process, the porous low dielectric film has a plurality of dangling bonds. Then, the wafer is placed in the supplementary instrument with hydrophobic reactive solution. Next, the hydrophobic protection film is formed on surface and sidewall of porous low-k dielectric film to improve the moisture absorption of porous low-k dielectric film and the leakage current is reduced in subsequently processes.Type: GrantFiled: June 26, 2001Date of Patent: July 9, 2002Assignee: United Microelectronics Corp.Inventors: Jung-Chih Hu, Lih-Juann Chen
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Patent number: 6083829Abstract: A method for fabricating a copper interconnect structure, using a low resistivity Cu.sub.3 Ge intermetallic layer, as an adhesive layer, has been developed. Following an in situ, CVD of a titanium nitride barrier layer, a germanium layer, and a copper layer, an anneal procedure is used to form the Cu.sub.3 Ge intermetallic layer, with the intermetallic layer, located between the underlying titanium nitride barrier layer, and the overlying copper layer. The Cu.sub.3 Ge intermetallic layer can also be formed in situ, during deposition, if the deposition temperature exceeds 150.degree. C. Cu.sub.3 Ge layer exhibits a resistivity of about 5E-6 ohm - cm. A second iteration of this invention allows a thick copper layer to be plated on a thin copper seed layer, only on the top surface of a semiconductor substrate. This iteration, also incorporating the low resistivity, Cu.sub.3 Ge intermetallic, and the adhesive layer, prevents copper from being plated on the beveled edge of the semiconductor substrate.Type: GrantFiled: May 22, 1998Date of Patent: July 4, 2000Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Jane-Bai Lai, Lih-Juann Chen, Chung-Shi Liu, Chen-Hua Douglas Yu
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Patent number: 6043148Abstract: A method of fabricating a metal plug. On a semiconductor substrate comprising a MOS device, a dielectric layer, and a via hole penetrating though the dielectric layer, a conformal titanium layer is formed on the dielectric layer and the via hole. A low temperature annealing is formed in a nitrogen environment, so that a surface of the titanium layer is transformed into a first thin titanium nitride layer. A conformal second titanium nitride layer is formed on the first thin titanium nitride layer by using collimator sputtering. A metal layer is formed and etched back on the second titanium nitride layer to form a metal plug.Type: GrantFiled: April 16, 1998Date of Patent: March 28, 2000Assignee: United Microelectronics Corp.Inventors: Yuan-Ching Peng, Lih-Juann Chen, Yu-Ru Yang, Win-Yi Hsieh, Yong-Fen Hsieh
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Patent number: 6022457Abstract: A method of manufacturing a cobalt suicide layer in the present invention has a silicon layer formation step. The silicon layer is formed at the interface between the cobalt layer and titanium layer, therefore the interface is smoother in this invention than in other conventional methods, and there are no voids formed at the interface. Moreover, consumption of the silicon can be controlled by adjusting the thickness of the silicon layer.Type: GrantFiled: March 18, 1998Date of Patent: February 8, 2000Assignee: United Microelectronics Corp.Inventors: Hsin-Yuan Huang, Yuan-Ching Peng, Lih-Juann Chen, Yong-Fen Hsieh
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Patent number: 6015749Abstract: A method for fabricating a copper interconnect structure, using a Cu.sub.3 Ge intermetallic layer, as an adhesive layer, has been developed. Following the deposition of a copper seed layer, an ion implantation procedure is performed, placing germanium ions in a copper seed layer. After deposition of a thick copper layer, an anneal cycle, performed before or after deposition of the thick copper layer, is used to create a Cu.sub.3 Ge intermetallic layer at the interface between a copper seed layer and a titanium nitride barrier layer. A second embodiment of this invention uses a tilted, germanium ion implantation procedure, used to avoid the placement of germanium ions in a copper seed layer, at the bottom of a contact hole, thus avoiding possible implantation damage, to active device regions, exposed in the bottom of the contact hole.Type: GrantFiled: May 4, 1998Date of Patent: January 18, 2000Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Chung-Shi Liu, Chen-Hua Douglas Yu, Jane-Bai Lai, Lih-Juann Chen
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Patent number: 5897373Abstract: The present invention relates to a method of manufacturing semiconductor components having a titanium nitride layer including the steps of providing a semiconductor substrate with a transistor including a gate and source/drain regions, depositing an insulating layer above the semiconductor substrate, etching the insulating layer to form an opening exposing the source/drain region below, depositing an ultra-thin titanium nitride layer having a grainy particulate profile and a thickness of about 0.5 nm to 2 nm around the edge and at the bottom of the opening, depositing a metallic layer over various aforementioned layers, and forming a metal silicide layer by heating the semiconductor substrate to allow the metallic layer to react with silicon on the semiconductor substrate surface.Type: GrantFiled: June 6, 1997Date of Patent: April 27, 1999Assignee: United Microelectronics Corp.Inventors: Yuan-Ching Peng, Lih-Juann Chen, Wen-Yi Hsieh, Jenn-Tarng Lin, Yong-Fen Hsieh