Patents by Inventor Lih Lin
Lih Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11955634Abstract: A particle structure of cathode material and a preparation method thereof is provided. Firstly, a precursor for forming a core is provided. The precursor includes at least nickel, cobalt and manganese. Secondly, a metal salt and a lithium ion compound are provided. The metal salt includes at least potassium, aluminum and sulfur. After that, the metal salt, the lithium ion compound and the precursor are mixed, and a mixture is formed. Finally, the mixture is subjected to a heat treatment step, and a cathode material particle structure is formed to include the core, a first coating layer coated on the core and a second coating layer coated on the first coating layer. The core includes potassium, aluminum and a Li-M-O based material. The first coating layer includes potassium and aluminum, and a potassium content of the first coating layer is higher than a potassium content of the core. The second coating layer includes sulfur.Type: GrantFiled: November 18, 2021Date of Patent: April 9, 2024Assignee: ADVANCED LITHIUM ELECTROCHEMISTRY CO., LTD.Inventors: Ching-Hao Yu, Nae-Lih Wu, Chia-Hsin Lin
-
Patent number: 11859237Abstract: A method for sizing a DNA molecule is disclosed, which comprises the following steps of: providing a DNA sizing device, comprising: a cover substrate; a substrate disposed on the cover substrate and comprising a first hole and a second hole; and a first slit-like channel disposed between the cover substrate and the substrate, wherein two ends of the first slit-like channel respectively connects to the first hole and the second hole; loading a sample comprising a DNA molecule to the first slit-like channel through the first hole, wherein the DNA molecule moves in a direction from the first hole to the second hole; detecting and recording an intensity and an area of a distribution of the DNA molecule; and analyzing the intensity and the area to obtain the size of a DNA molecule.Type: GrantFiled: November 8, 2019Date of Patent: January 2, 2024Assignee: ACADEMIA SINICAInventors: Chia-Fu Chou, Jia-Wei Yeh, Yii-Lih Lin
-
Publication number: 20200149088Abstract: A method for sizing a DNA molecule is disclosed, which comprises the following steps of: providing a DNA sizing device, comprising: a cover substrate; a substrate disposed on the cover substrate and comprising a first hole and a second hole; and a first slit-like channel disposed between the cover substrate and the substrate, wherein two ends of the first slit-like channel respectively connects to the first hole and the second hole; loading a sample comprising a DNA molecule to the first slit-like channel through the first hole, wherein the DNA molecule moves in a direction from the first hole to the second hole; detecting and recording an intensity and an area of a distribution of the DNA molecule; and analyzing the intensity and the area to obtain the size of a DNA molecule.Type: ApplicationFiled: November 8, 2019Publication date: May 14, 2020Inventors: Chia-Fu CHOU, Jia-Wei YEH, Yii-Lih LIN
-
Patent number: 10644501Abstract: A driving circuit controlling a voltage level of an input/output pad and having an electrostatic discharge (ESD) protection function comprises a detector, a controller, and a release control element. The detector is configured to couple to a power terminal and the input/output pad. The controller is coupled to the detector. The release control element is coupled to the power terminal or the input/output pad and coupled to the controller. When an ESD event occurs at the power terminal or the input/output pad, the detector activates the controller to a control signal to control the voltage level of the input/output pad.Type: GrantFiled: July 14, 2016Date of Patent: May 5, 2020Assignee: Vanguard International Semiconductor CorporationInventors: Shao-Chang Huang, Shi-Hsiang Lu, Geeng-Lih Lin
-
Patent number: 10334010Abstract: A transmission rate determination method for streaming media is disclosed. The transmission rate determination method includes the following steps: collecting a location message, a time message, a communication parameter information and a transmission bit rate of a mobile device; updating a database of streaming throughput according to the location message, the time message, the communication parameter information and the transmission bit rate; wherein the database of streaming throughput includes information regarding a plurality of regions. The information of each of the plurality of regions includes an average transmission rate. The average transmission rate is related to the location message, the time message, the communication parameter information and the transmission bit rate.Type: GrantFiled: December 22, 2016Date of Patent: June 25, 2019Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chun-Hsien Wu, Chien-Peng Ho, Ping-Lih Lin
-
Publication number: 20190116511Abstract: An embodiment of a data sensing method includes: dynamically establishing and dynamically updating in a carrier status database at least one carrier status information of at least one carrier that received; based on at least one sensing task requirement and at least the carrier status information of at least one carrier that received, dynamically generating and/or adjusting at least one sensing task; and assigning at least the sensing task to the at least one carrier.Type: ApplicationFiled: December 27, 2017Publication date: April 18, 2019Inventors: Chun-Hsien WU, Chien-Peng HO, Ping-Lih LIN
-
Patent number: 10177135Abstract: An electrostatic discharge protection circuit is provided. The electrostatic discharge protection circuit includes a first metal-oxide-semiconductor (MOS) transistor, a second MOS transistor, and a third MOS transistor. The first MOS transistor is coupled between a power terminal and a ground terminal. The first MOS transistor has a control electrode terminal coupled to a first node to receive a first signal. The second MOS transistor has a control electrode terminal and a first electrode terminal both coupled to the first node and a second electrode terminal coupled to a bulk of the first MOS transistor. The third MOS transistor has a control electrode terminal coupled to a second node to receive a second node, a first electrode terminal coupled to the first node, and a second electrode terminal coupled to the bulk of the first MOS transistor. The first signal is inverse to the second signal.Type: GrantFiled: May 18, 2016Date of Patent: January 8, 2019Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Shao-Chang Huang, Chun-Chien Tsai, Yeh-Ning Jou, Geeng-Lih Lin
-
Publication number: 20180152493Abstract: A transmission rate determination method for streaming media is disclosed. The transmission rate determination method includes the following steps: collecting a location message, a time message, a communication parameter information and a transmission bit rate of a mobile device; updating a database of streaming throughput according to the location message, the time message, the communication parameter information and the transmission bit rate; wherein the database of streaming throughput includes information regarding a plurality of regions. The information of each of the plurality of regions includes an average transmission rate. The average transmission rate is related to the location message, the time message, the communication parameter information and the transmission bit rate.Type: ApplicationFiled: December 22, 2016Publication date: May 31, 2018Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chun-Hsien WU, Chien-Peng HO, Ping-Lih LIN
-
Patent number: 9958396Abstract: A sensing device applied to an analyte molecule of a liquid sample and a buffer flow has at least one first inlet, at least one second inlet, a micro-flow channel, and at least one immobilization element. The first inlet is for inputting the liquid sample. The second inlet is for inputting the buffer flow. The micro-flow channel communicates with the first inlet and the second inlet. The immobilization element is for immobilizing sensing molecules for the analyte molecules. The analyte sample flow and the buffer flow, in the reverse direction, in the micro-flow channel enable the association and disassociation kinetics to be obtained. The present invention further provides a sensing system and a sensing method using the sensing device.Type: GrantFiled: May 27, 2015Date of Patent: May 1, 2018Assignees: Academia Sinica, Centre National De La Recherche ScientifiqueInventors: Chia-Fu Chou, Thierry Leichle, Yii-Lih Lin, Pattamon Teerapanich
-
Patent number: 9893516Abstract: An ESD protection circuit, which is coupled between either an I/O pad or a power pad and a ground terminal, includes a non-snapback device and a snapback device. When the voltage across the non-snapback device is not less than the non-snapback trigger voltage, the non-snapback device is turned on. When the voltage across the snapback device is not less than the snapback trigger voltage, the snapback device is turned on, and the voltage across the snapback device is held at the snapback holding voltage, in which the snapback holding voltage is less than the snapback trigger voltage. The non-snapback device and the snapback device are cascaded.Type: GrantFiled: December 3, 2015Date of Patent: February 13, 2018Assignee: Vanguard International Semiconductor CorporationInventors: Yeh-Ning Jou, Geeng-Lih Lin
-
Publication number: 20180019741Abstract: A driving circuit controlling a voltage level of an input/output pad and having an electrostatic discharge (ESD) protection function comprises a detector, a controller, and a release control element. The detector is configured to couple to a power terminal and the input/output pad. The controller is coupled to the detector. The release control element is coupled to the power terminal or the input/output pad and coupled to the controller. When an ESD event occurs at the power terminal or the input/output pad, the detector activates the controller to a control signal to control the voltage level of the input/output pad.Type: ApplicationFiled: July 14, 2016Publication date: January 18, 2018Applicant: Vanguard International Semiconductor CorporationInventors: Shao-Chang HUANG, Shi-Hsiang LU, Geeng-Lih LIN
-
Publication number: 20170338221Abstract: An electrostatic discharge protection circuit is provided. The electrostatic discharge protection circuit includes a first metal-oxide-semiconductor (MOS) transistor, a second MOS transistor, and a third MOS transistor. The first MOS transistor is coupled between a power terminal and a ground terminal. The first MOS transistor has a control electrode terminal coupled to a first node to receive a first signal. The second MOS transistor has a control electrode terminal and a first electrode terminal both coupled to the first node and a second electrode terminal coupled to a bulk of the first MOS transistor. The third MOS transistor has a control electrode terminal coupled to a second node to receive a second node, a first electrode terminal coupled to the first node, and a second electrode terminal coupled to the bulk of the first MOS transistor. The first signal is inverse to the second signal.Type: ApplicationFiled: May 18, 2016Publication date: November 23, 2017Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Shao-Chang HUANG, Chun-Chien TSAI, Yeh-Ning JOU, Geeng-Lih LIN
-
Patent number: 9722097Abstract: A semiconductor device is provided. The semiconductor device includes a substrate; a well region disposed in the substrate; an isolation structure surrounding an active region in the well region; a source region disposed in the well region; a drain region disposed in the well region; a second conductive type first doped region disposed in the well region and disposed along a periphery of the active region; a second conductive type second doped region disposed in the well region and under the source region, the drain region and the second conductive type first doped region, wherein the second conductive type second doped region is in direct contact with the second conductive type first doped region; a source electrode; a drain electrode and a gate electrode. The present disclosure also provides a method for manufacturing the semiconductor device.Type: GrantFiled: September 16, 2015Date of Patent: August 1, 2017Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Karuna Nidhi, Federico Agustin Altolaguirre, Ming-Dou Ker, Geeng-Lih Lin
-
Publication number: 20170163031Abstract: An ESD protection circuit, which is coupled between either an I/O pad or a power pad and a ground terminal, includes a non-snapback device and a snapback device. When the voltage across the non-snapback device is not less than the non-snapback trigger voltage, the non-snapback device is turned on. When the voltage across the snapback device is not less than the snapback trigger voltage, the snapback device is turned on, and the voltage across the snapback device is held at the snapback holding voltage, in which the snapback holding voltage is less than the snapback trigger voltage. The non-snapback device and the snapback device are cascaded.Type: ApplicationFiled: December 3, 2015Publication date: June 8, 2017Applicant: Vanguard International Semiconductor CorporationInventors: Yeh-Ning JOU, Geeng-Lih LIN
-
Patent number: 9633992Abstract: An ESD protection device is provided. Each of a first and a second well has a first conductive type. Each of a first and a second doping region has a second conductive type and is formed in the first well. A third doping region has the first conductive type. A fourth doping region has the second conductive type. The third and fourth doping regions are formed in the second doping region. Each of a fifth and a sixth doping region has the second conductive type and is formed in the second well. A seventh doping region has the first conductive type. An eighth doping region has the second conductive type. The seventh and eighth doping region are formed in the sixth doping region. A first and a second trigger gate are formed on the first and second wells and partially cover the second and sixth doping regions respectively.Type: GrantFiled: February 23, 2016Date of Patent: April 25, 2017Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Yeh-Jen Huang, Yeh-Ning Jou, Geeng-Lih Lin
-
Publication number: 20170077316Abstract: A semiconductor device is provided. The semiconductor device includes a substrate; a well region disposed in the substrate; an isolation structure surrounding an active region in the well region; a source region disposed in the well region; a drain region disposed in the well region; a second conductive type first doped region disposed in the well region and disposed along a periphery of the active region; a second conductive type second doped region disposed in the well region and under the source region, the drain region and the second conductive type first doped region, wherein the second conductive type second doped region is in direct contact with the second conductive type first doped region; a source electrode; a drain electrode and a gate electrode. The present disclosure also provides a method for manufacturing the semiconductor device.Type: ApplicationFiled: September 16, 2015Publication date: March 16, 2017Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Karuna NIDHI, Federico Agustin ALTOLAGUIRRE, Ming-Dou KER, Geeng-Lih LIN
-
Patent number: 9443943Abstract: The invention provides a semiconductor device. A buried layer is formed in a substrate. A first deep trench contact structure is formed in the substrate. The first deep trench contact structure comprises a conductor and a liner layer formed on a sidewall of the conductor. A bottom surface of the first deep trench contact structure is in contact with the buried layer.Type: GrantFiled: November 12, 2014Date of Patent: September 13, 2016Assignee: Vanguard International Semiconductor CorporationInventors: Geeng-Lih Lin, Kwang-Ming Lin, Shang-Hui Tu, Jui-Chun Chang
-
Patent number: 9437591Abstract: A cross-domain electrostatic protection device having four embedded silicon controlled rectifiers (a QSCR structure) embedded in a single cell. Two grounded-gate NMOS transistors are embedded into the cross-domain electrostatic protection device for reducing trigger voltage of the QSCR structure. Furthermore, an external trigger circuit and a bias circuit are applied to the cross-domain electrostatic protection device to reduce trigger voltage of the QSCR structure and leakage current.Type: GrantFiled: September 9, 2015Date of Patent: September 6, 2016Assignee: Vanguard International Semiconductor CorporationInventors: Karuna Nidhi, Federico Agustin Altolaguirre, Ming-Dou Ker, Geeng-Lih Lin
-
Publication number: 20150346104Abstract: A sensing device applied to an analyte molecule of a liquid sample and a buffer flow has at least one first inlet, at least one second inlet, a micro-flow channel, and at least one immobilization element. The first inlet is for inputting the liquid sample. The second inlet is for inputting the buffer flow. The micro-flow channel communicates with the first inlet and the second inlet. The immobilization element is for immobilizing sensing molecules for the analyte molecules. The analyte sample flow and the buffer flow, in the reverse direction, in the micro-flow channel enable the association and disassociation kinetics to be obtained. The present invention further provides a sensing system and a sensing method using the sensing device.Type: ApplicationFiled: May 27, 2015Publication date: December 3, 2015Inventors: Chia-Fu CHOU, Thierry LEICHLE, Yii-Lih LIN, Pattamon TEERAPANICH
-
Publication number: 20150137327Abstract: The invention provides a semiconductor device. A buried layer is formed in a substrate. A first deep trench contact structure is formed in the substrate. The first deep trench contact structure comprises a conductor and a liner layer formed on a sidewall of the conductor. A bottom surface of the first deep trench contact structure is in contact with the buried layer.Type: ApplicationFiled: November 12, 2014Publication date: May 21, 2015Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Geeng-Lih LIN, Kwang-Ming LIN, Shang-Hui TU, Jui-Chun CHANG