Patents by Inventor Lily Jielu Zhang

Lily Jielu Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • PHASE ALIGNING AND CALIBRATING CLOCKS FROM ONE PHASE LOCK LOOP (PLL) FOR A TWO-CHIP DIE MODULE
    Publication number: 20230393610
    Abstract: A two-chip die module with minimal chip-to-chip clock skew is provided. The two-chip die module includes a common substrate, first and second chips operably disposed on the common substrate to be communicative in parallel with one another and a single phase lock loop (PLL). The PLL is disposed within one of the first and second chips to provide a source for a common clock signal for the first and second chips. PLL signals of the PLL to the first and second chips are nearly equal and clock sample signals of the first and second chips are nearly equal.
    Type: Application
    Filed: August 24, 2023
    Publication date: December 7, 2023
    Inventors: Douglas J. Malone, Andreas H. A. Arp, Franklin M. Baez, Daniel M. Dreps, Jason Lee Frankel, Chad Andrew Marquart, Ching Lung Tong, Lily Jielu Zhang
  • Phase aligning and calibrating clocks from one phase lock loop (PLL) for a two-chip die module
    Patent number: 11775004
    Abstract: A two-chip die module with minimal chip-to-chip clock skew is provided. The two-chip die module includes a common substrate, first and second chips operably disposed on the common substrate to be communicative in parallel with one another and a single phase lock loop (PLL). The PLL is disposed within one of the first and second chips to provide a source for a common clock signal for the first and second chips. PLL signals of the PLL to the first and second chips are nearly equal and clock sample signals of the first and second chips are nearly equal.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: October 3, 2023
    Assignee: International Business Machines Corporation
    Inventors: Douglas J. Malone, Andreas H. A. Arp, Franklin M. Baez, Daniel M. Dreps, Jason Lee Frankel, Chad Andrew Marquart, Ching Lung Tong, Lily Jielu Zhang
  • PHASE ALIGNING AND CALIBRATING CLOCKS FROM ONE PHASE LOCK LOOP (PLL) FOR A TWO-CHIP DIE MODULE
    Publication number: 20230085155
    Abstract: A two-chip die module with minimal chip-to-chip clock skew is provided. The two-chip die module includes a common substrate, first and second chips operably disposed on the common substrate to be communicative in parallel with one another and a single phase lock loop (PLL). The PLL is disposed within one of the first and second chips to provide a source for a common clock signal for the first and second chips. PLL signals of the PLL to the first and second chips are nearly equal and clock sample signals of the first and second chips are nearly equal.
    Type: Application
    Filed: September 10, 2021
    Publication date: March 16, 2023
    Inventors: Douglas J. Malone, Andreas H. A. Arp, Franklin M. Baez, Daniel M. Dreps, Jason Lee Frankel, Chad Andrew Marquart, Ching Lung Tong, Lily Jielu Zhang