Patents by Inventor Lily Springer
Lily Springer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9865584Abstract: A contact array optimization scheme for ESD devices. In one embodiment, contact apertures patterned through a pre-metal dielectric layer over active areas may be selectively modified in size, shape, placement and the like, to increase ESD protection performance, e.g., such as maximizing the transient current density, etc., in a standard ESD rating test.Type: GrantFiled: November 4, 2016Date of Patent: January 9, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: He Lin, Kun Chen, Chao Wu, Dening Wang, Lily Springer, Andy Strachan, Gang Xue
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Publication number: 20180006013Abstract: A contact array optimization scheme for ESD devices. In one embodiment, contact apertures patterned through a pre-metal dielectric layer over active areas may be selectively modified in size, shape, placement and the like, to increase ESD protection performance, e.g., such as maximizing the transient current density, etc., in a standard ESD rating test.Type: ApplicationFiled: November 4, 2016Publication date: January 4, 2018Inventors: He LIN, Kun CHEN, Chao WU, Dening WANG, Lily SPRINGER, Andy STRACHAN, Gang XUE
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Patent number: 8664080Abstract: A method for forming a vertical electrostatic discharge (ESD) protection device includes depositing a multi-layer n-type epitaxial layer on a substrate having p-type surface including first epitaxial depositing to form a first n-type epitaxial layer on the p-type surface, and second epitaxial depositing to form a second n-type epitaxial layer formed on the first n-type epitaxial layer. The first type epitaxial layer has a peak doping level which is at least double that of the second n-type epitaxial layer. A p+ layer is formed on the second n-type epitaxial layer. An etch step etches through the p+ layer and multi-layer n-type epitaxial layer to reach the substrate to form a trench. The trench is filled with a filler material to form a trench isolation region. A metal contact is formed on the p+ layer for providing contact to the p+ layer.Type: GrantFiled: May 22, 2012Date of Patent: March 4, 2014Assignee: Texas Instruments IncorporatedInventors: Toshiyuki Tani, Hiroshi Yamasaki, Kentaro Takahashi, Lily Springer
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Publication number: 20120299146Abstract: A method for forming a vertical electrostatic discharge (ESD) protection device includes depositing a multi-layer n-type epitaxial layer on a substrate having p-type surface including first epitaxial depositing to form a first n-type epitaxial layer on the p-type surface, and second epitaxial depositing to form a second n-type epitaxial layer formed on the first n-type epitaxial layer. The first type epitaxial layer has a peak doping level which is at least double that of the second n-type epitaxial layer. A p+ layer is formed on the second n-type epitaxial layer. An etch step etches through the p+ layer and multi-layer n-type epitaxial layer to reach the substrate to form a trench. The trench is filled with a filler material to form a trench isolation region. A metal contact is formed on the p+ layer for providing contact to the p+ layer.Type: ApplicationFiled: May 22, 2012Publication date: November 29, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: TOSHIYUKI TANI, HIROSHI YAMASAKI, KENTARO TAKAHASHI, LILY SPRINGER
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Publication number: 20070205435Abstract: Disclosed are apparatus and methods for designing electrical contact for a bipolar emitter structure. The area of an emitter structure (106, 306, 400, 404) and the required current density throughput of an electrical contact structure (108, 308, 402, 406) are determined. A required electrical contact area is determined based on the required current density, and the electrical contact structure is then designed to minimize the required electrical contact area with respect to the emitter structure area.Type: ApplicationFiled: May 8, 2007Publication date: September 6, 2007Applicant: Texas Instruments IncorporatedInventors: Joe Trogolo, Tathagata Chatterlee, Lily Springer, Jeff Smith
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Patent number: 7226835Abstract: Disclosed are apparatus and methods for designing electrical contact for a bipolar emitter structure. The area of an emitter structure (106, 306, 400, 404) and the required current density throughput of an electrical contact structure (108, 308, 402, 406) are determined. A required electrical contact area is determined based on the required current density, and the electrical contact structure is then designed to minimize the required electrical contact area with respect to the emitter structure area.Type: GrantFiled: July 15, 2002Date of Patent: June 5, 2007Assignee: Texas Instruments IncorporatedInventors: Joe Trogolo, Tathagata Chatterlee, Lily Springer, Jeff Smith
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Publication number: 20070033556Abstract: Validation of at least some of a proposed semiconductor design layout is disclosed. According to one or more aspects of the present invention, a first voltage dependent design rule is applied to an edge of an area of the layout if the edge is not covered by a pseudo layer. A second voltage dependent design rule is, on the other hand, applied to the edge of the area if the edge is covered by the pseudo layer.Type: ApplicationFiled: August 8, 2005Publication date: February 8, 2007Inventors: Lily Springer, Haim Horovitz, Robert Shaw, Sameer Pendharkar, Wen-Hwa Chu, Paul Mannas
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Patent number: 7164174Abstract: A method of forming a bipolar transistor device, and more particularly a vertical poly-emitter PNP transistor, as part of a BiCMOS type manufacturing process is disclosed. The formation of the PNP transistor during a CMOS/DMOS fabrication process requires merely one additional mask to facilitate formation of a very small emitter in a portion of an N-type surface layer of a double diffused well (DWELL). Unlike conventional PNP transistors, a separate mask is not required to establish the base of the transistor as the transistor base is formed from a portion of the double diffused well and the DWELL includes a P-type body layer formed via implantation through the same opening in the same mask utilized to establish the N-type surface layer of the double diffused well. The base is also thin thus improving the transistor's frequency and gain.Type: GrantFiled: July 28, 2005Date of Patent: January 16, 2007Assignee: Texas Instruments IncorporatedInventor: Lily Springer
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Publication number: 20060189089Abstract: The present invention provides an integrated high voltage capacitor, a method of manufacture therefore, and an integrated circuit chip including the same. The integrated high voltage capacitor, among other features, includes a first capacitor plate (120) located over or in a semiconductor substrate (105), and an insulator (130) located over the first capacitor plate (120), at least a portion of the insulator (130) comprising an interlevel dielectric layer (135, 138, 143, or 148). The integrated high voltage capacitor further includes capacitance uniformity structures (910) located at least partially within the insulator (130) and a second capacitor plate (160) located over the insulator (130).Type: ApplicationFiled: October 13, 2005Publication date: August 24, 2006Applicant: Texas Instruments Inc.Inventors: David Larkin, Lily Springer, Makoto Takemura, Ashish Gokhale, Dhaval Saraiya
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Publication number: 20060186450Abstract: The present invention provides an integrated high voltage capacitor, a method of manufacture therefore, and an integrated circuit chip including the same. The integrated high voltage capacitor, among other features, includes a first capacitor plate (120) located over or in a semiconductor substrate (105), and an insulator (130) located over the first capacitor plate (120), at least a portion of the insulator (130) comprising an interlevel dielectric layer (135, 138, 143, or 148). The integrated high voltage capacitor further includes a second capacitor plate (160) located over the insulator (130).Type: ApplicationFiled: October 13, 2005Publication date: August 24, 2006Applicant: Texas Instruments Inc.Inventors: David Larkin, Lily Springer, Makoto Takemura, Ashish Gokhale, Dhaval Saraiya
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Publication number: 20050258453Abstract: A method of forming a bipolar transistor device, and more particularly a vertical poly-emitter PNP transistor, as part of a BiCMOS type manufacturing process is disclosed. The formation of the PNP transistor during a CMOS/DMOS fabrication process requires merely one additional mask to facilitate formation of a very small emitter in a portion of an N-type surface layer of a double diffused well (DWELL). Unlike conventional PNP transistors, a separate mask is not required to establish the base of the transistor as the transistor base is formed from a portion of the double diffused well and the DWELL includes a P-type body layer formed via implantation through the same opening in the same mask utilized to establish the N-type surface layer of the double diffused well. The base is also thin thus improving the transistor's frequency and gain.Type: ApplicationFiled: July 28, 2005Publication date: November 24, 2005Inventor: Lily Springer
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Patent number: 6958269Abstract: A method for manufacturing a memory device includes forming an oxide layer adjacent a substrate. A floating gate layer is formed and disposed outwardly from the oxide layer. A dielectric layer is formed, such that it is disposed outwardly from the floating gate layer. Then, a conductive material layer is formed and disposed outwardly from the dielectric layer, wherein the conductive material layer forms a control gate that is substantially isolated from the floating gate layer by the dielectric layer.Type: GrantFiled: June 24, 2002Date of Patent: October 25, 2005Assignee: Texas Instruments IncorporatedInventors: Josef Czeslaw Mitros, Imran Khan, Lily Springer
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Patent number: 6949424Abstract: A method of forming a bipolar transistor device, and more particularly a vertical poly-emitter PNP transistor, as part of a BiCMOS type manufacturing process is disclosed. The formation of the PNP transistor during a CMOS/DMOS fabrication process requires merely one additional mask to facilitate formation of a very small emitter in a portion of an N-type surface layer of a double diffused well (DWELL). Unlike conventional PNP transistors, a separate mask is not required to establish the base of the transistor as the transistor base is formed from a portion of the double diffused well and the DWELL includes a P-type body layer formed via implantation through the same opening in the same mask utilized to establish the N-type surface layer of the double diffused well. The base is also thin thus improving the transistor's frequency and gain.Type: GrantFiled: August 28, 2003Date of Patent: September 27, 2005Assignee: Texas Instruments IncorporatedInventor: Lily Springer
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Patent number: 6869851Abstract: A method of forming two regions having differing depths using a single implantation process is provided. A mask having two openings associated therewith is formed over a semiconductor body, wherein one of the openings has a size larger than an implantation design rule, and the other opening has a size smaller than the design rule. An implant is performed into the semiconductor body through the implant mask, resulting in two distinct doped regions, wherein the region associated with the larger opening has more dopant than the region associated with the smaller opening. Subsequent activation and thermal processing results in the one region diffusing a greater amount than the second region, thereby resulting in two regions formed concurrently having different depths.Type: GrantFiled: January 20, 2004Date of Patent: March 22, 2005Assignee: Texas Instruments IncorporatedInventors: Joe R. Trogolo, Lily Springer, Jeff Smith, Sheldon Haynie
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Publication number: 20050045948Abstract: A method of forming a bipolar transistor device, and more particularly a vertical poly-emitter PNP transistor, as part of a BiCMOS type manufacturing process is disclosed. The formation of the PNP transistor during a CMOS/DMOS fabrication process requires merely one additional mask to facilitate formation of a very small emitter in a portion of an N-type surface layer of a double diffused well (DWELL). Unlike conventional PNP transistors, a separate mask is not required to establish the base of the transistor as the transistor base is formed from a portion of the double diffused well and the DWELL includes a P-type body layer formed via implantation through the same opening in the same mask utilized to establish the N-type surface layer of the double diffused well. The base is also thin thus improving the transistor's frequency and gain.Type: ApplicationFiled: August 28, 2003Publication date: March 3, 2005Inventor: Lily Springer
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Publication number: 20040152288Abstract: A method of forming two regions having differing depths using a single implantation process is provided. A mask having two openings associated therewith is formed over a semiconductor body, wherein one of the openings has a size larger than an implantation design rule, and the other opening has a size smaller than the design rule. An implant is performed into the semiconductor body through the implant mask, resulting in two distinct doped regions, wherein the region associated with the larger opening has more dopant than the region associated with the smaller opening. Subsequent activation and thermal processing results in the one region diffusing a greater amount than the second region, thereby resulting in two regions formed concurrently having different depths.Type: ApplicationFiled: January 20, 2004Publication date: August 5, 2004Inventors: Joe R. Trogolo, Lily Springer, Jeff Smith, Sheldon Hayrie
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Patent number: 6747308Abstract: An EEPROM (100) comprises a source region (122), a drain region (120); and a polysilicon layer (110). The polysilicon layer (110) comprises a floating gate comprising at least one polysilicon finger (112A-112E) operatively coupling the source region (122) and drain region (120) and a control gate comprising at least one of the polysilicon fingers (112A-112E) capacitively coupled to the floating gate. The EEPROM (100) has a substantially reduce area compared to prior art EEPROM since an n-well region is eliminated.Type: GrantFiled: December 30, 2002Date of Patent: June 8, 2004Assignee: Texas Instruments IncorporatedInventors: Jozef C. Mitros, Lily Springer, Roland Bucksch
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Patent number: 6716709Abstract: A method of forming two regions having differing depths using a single implantation process is provided. A mask having two openings associated therewith is formed over a semiconductor body, wherein one of the openings has a size larger than an implantation design rule, and the other opening has a size smaller than the design rule. An implant is performed into the semiconductor body through the implant mask, resulting in two distinct doped regions, wherein the region associated with the larger opening has more dopant than the region associated with the smaller opening. Subsequent activation and thermal processing results in the one region diffusing a greater amount than the second region, thereby resulting in two regions formed concurrently having different depths.Type: GrantFiled: December 31, 2002Date of Patent: April 6, 2004Assignee: Texas Instruments IncorporatedInventors: Lily Springer, Jeff Smith, Sheldon Haynie, Joe R. Trogolo
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Publication number: 20040007716Abstract: Disclosed are apparatus and methods for designing electrical contact for a bipolar emitter structure. The area of an emitter structure (106, 306, 400, 404) and the required current density throughput of an electrical contact structure (108, 308, 402, 406) are determined. A required electrical contact area is determined based on the required current density, and the electrical contact structure is then designed to minimize the required electrical contact area with respect to the emitter structure area.Type: ApplicationFiled: July 15, 2002Publication date: January 15, 2004Inventors: Joe Trogolo, Tathagata Chatterlee, Lily Springer, Jeff Smith
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Publication number: 20030235949Abstract: A method for manufacturing a memory device includes forming an oxide layer adjacent a substrate. A floating gate layer is formed and disposed outwardly from the oxide layer. A dielectric layer is formed, such that it is disposed outwardly from the floating gate layer. Then, a conductive material layer is formed and disposed outwardly from the dielectric layer, wherein the conductive material layer forms a control gate that is substantially isolated from the floating gate layer by the dielectric layer.Type: ApplicationFiled: June 24, 2002Publication date: December 25, 2003Applicant: Texas Instruments IncorporatedInventors: Josef Czeslaw Mitros, Imran Khan, Lily Springer