Patents by Inventor Lin Chiu

Lin Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240169903
    Abstract: An electronic device may include an electronic display having a gate-on-array (GOA) that generates gate signals in response to an activation signal, pixels that activate in response to a combination of the gate signals and data signals indicative of image data, and sensing circuitry. The sensing circuitry may measure a characteristic response of a gate signal a characteristic response of one or more pixels, or both and compare the characteristic responses to baselines. The electronic device may also include compensation circuitry that applies a compensation to the activation signal and/or to the image data based on the comparisons between the characteristic responses and the baselines.
    Type: Application
    Filed: September 19, 2023
    Publication date: May 23, 2024
    Inventors: Sun-Il Chang, Kwang Soon Park, Hao-Lin Chiu, Jie Won Ryu, Hyunsoo Kim, Hyunwoo Nho, Wei Xiong, Patrick R. Cruce
  • Publication number: 20240162318
    Abstract: A thin film transistor includes a gate electrode embedded in an insulating layer that overlies a substrate, a gate dielectric overlying the gate electrode, an active layer comprising a compound semiconductor material and overlying the gate dielectric, and a source electrode and drain electrode contacting end portions of the active layer. The gate dielectric may have thicker portions over interfaces with the insulating layer to suppress hydrogen diffusion therethrough. Additionally or alternatively, a passivation capping dielectric including a dielectric metal oxide material may be interposed between the active layer and a dielectric layer overlying the active layer to suppress hydrogen diffusion therethrough.
    Type: Application
    Filed: January 26, 2024
    Publication date: May 16, 2024
    Inventors: Min-Kun DAI, Wei-Gang CHIU, I-Cheng CHANG, Cheng-Yi WU, Han-Ting TSAI, Tsann LIN, Chung-Te LIN
  • Patent number: 11984090
    Abstract: The present invention provides four-particle electrophoretic displays with improved driving methods to achieve better color separation between adjacent pixel electrodes. The driving methods improve the color state performance when a first pixel is displaying a mixed state of a first highly-charged particle and a second lower-charged particle of the opposite polarity, while a neighboring pixel is displaying a state of a second highly-charged particle having the opposite polarity to the first highly-charged particle. The particles can be, for example, all reflective or one type of particle can be partially light transmissive.
    Type: Grant
    Filed: November 30, 2022
    Date of Patent: May 14, 2024
    Assignee: E Ink Corporation
    Inventors: Chih-Yu Cheng, Craig Lin, Ning-Wei Jan, Chen-Kai Chiu, Feng-Shou Lin
  • Publication number: 20240150656
    Abstract: A liquid crystal polymer, composition, liquid crystal polymer film, laminated material and method of forming liquid crystal polymer film are provided. The liquid crystal polymer includes a first repeating unit, a second repeating unit, a third repeating unit, a fourth repeating unit, and a fifth repeating unit. The first repeating unit has a structure of Formula (I), the second repeating unit has a structure of Formula (II), the third repeating unit has a structure of Formula (III), the fourth repeating unit has a structure of Formula (IV), and the fifth repeating unit has a structure of Formula (V), a structure of Formula (VI), or a structure of Formula (VII) wherein A1, A2, A3, A4, X1, Z1, R1, R2, R3 and Q are as defined in the specification.
    Type: Application
    Filed: September 22, 2023
    Publication date: May 9, 2024
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yu-Lin CHU, Jen-Chun CHIU, Po-Hsien HO, Yu-Min HAN, Meng-Hsin CHEN, Chih-Hsiang LIN
  • Publication number: 20240144863
    Abstract: An electronic device able to be operated with a first state and a second state includes a substrate and electronic units. In a top view, the substrate has a first area in the first state and a second area in the second state, and the second area is greater than the first area. The electronic units are disposed on the substrate. The number of the electronic units being in a mode of ON in the second state is greater than that in the first state. The electronic device has a PPA_1 that is defined as a number of the electronic units being in the mode of ON per unit area of the substrate while in the first state, and a PPA_2 that is defined as a number of the electronic units being in the mode of ON per unit area of the substrate while in the second state, 1.5×PPA_1?PPA_2?0.5×PPA_1.
    Type: Application
    Filed: January 4, 2024
    Publication date: May 2, 2024
    Applicant: InnoLux Corporation
    Inventors: Yuan-Lin Wu, Chan-Feng Chiu, Kuan-Feng Lee
  • Patent number: 11966544
    Abstract: An electronic device may have a display with touch sensors. One or more shielding layers may be interposed between the display and the touch sensors. The display may include transistors with gate conductors, a first planarization layer formed over the gate conductors, one or more contacts formed in a first source-drain layer within the first planarization layer, a second planarization layer formed on the first planarization layer, one or more data lines formed in a second source-drain layer within the second planarization layer, a third planarization layer formed on the second planarization layer, and a data line shielding structure formed at least partly in a third source-drain layer within the third planarization layer. The data line shielding structure may be a routing line, a blanket layer, a mesh layer formed in one or more metal layers, and/or a data line covering another data line.
    Type: Grant
    Filed: May 25, 2023
    Date of Patent: April 23, 2024
    Assignee: Apple Inc.
    Inventors: Shinya Ono, Suhwan Moon, Dong-Gwang Ha, Jiaxi Hu, Hao-Lin Chiu, Kwang Soon Park, Hassan Edrees, Wen-I Hsieh, Jiun-Jye Chang, Chin-Wei Lin, Kyung Wook Kim
  • Publication number: 20240124706
    Abstract: A liquid crystal polymer, composition, liquid crystal polymer film, laminated material and method of forming liquid crystal polymer film are provided. The liquid crystal polymer includes a first repeating unit, a second repeating unit, a third repeating unit, and a fourth repeating unit. The first repeating unit has a structure of Formula (I), the second repeating unit has a structure of Formula (II), the third repeating unit has a structure of Formula (III), and the fourth repeating unit has a structure of Formula (IV), a structure of Formula (V) or a structure of Formula (VI) wherein A1, A2, A3, Z1, R1, R2, R3 and Q are as defined in the specification.
    Type: Application
    Filed: September 22, 2023
    Publication date: April 18, 2024
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yu-Lin CHU, Jen-Chun CHIU, Po- Hsien HO, Yu-Min HAN, Meng-Hsin CHEN, Chih-Hsiang LIN
  • Publication number: 20240111210
    Abstract: A method of manufacturing a semiconductor device includes the following steps. A photoresist layer is formed over a material layer on a substrate. The photoresist layer has a composition including a solvent and a first photo-active compound dissolved in the solvent. The first photo-active compound is represented by the following formula (A1) or formula (A2): Zr12O8(OH)14(RCO2)18 ??Formula (A1); or Hf6O4(OH)6(RCO2)10 ??Formula (A2). R in the formula (A1) and R in the formula (A2) each include one of the following formulae (1) to (6): The photoresist layer is patterned. The material layer is etched using the photoresist layer as an etch mask.
    Type: Application
    Filed: May 9, 2023
    Publication date: April 4, 2024
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TSING HUA UNIVERSITY
    Inventors: Jui-Hsiung LIU, Pin-Chia LIAO, Ting-An LIN, Ting-An SHIH, Yu-Fang TSENG, Burn Jeng LIN, Tsai-Sheng GAU, Po-Hsiung CHEN, Po-Wen CHIU
  • Patent number: 11935935
    Abstract: A thin film transistor includes a gate electrode embedded in an insulating layer that overlies a substrate, a gate dielectric overlying the gate electrode, an active layer comprising a compound semiconductor material and overlying the gate dielectric, and a source electrode and drain electrode contacting end portions of the active layer. The gate dielectric may have thicker portions over interfaces with the insulating layer to suppress hydrogen diffusion therethrough. Additionally or alternatively, a passivation capping dielectric including a dielectric metal oxide material may be interposed between the active layer and a dielectric layer overlying the active layer to suppress hydrogen diffusion therethrough.
    Type: Grant
    Filed: November 11, 2021
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Min-Kun Dai, Wei-Gang Chiu, I-Cheng Chang, Cheng-Yi Wu, Han-Ting Tsai, Tsann Lin, Chung-Te Lin
  • Publication number: 20240086633
    Abstract: A method for generating and outputting a message is implemented using an electronic device the stores a computer program product and a text database. The text database includes a main message template, a template text that includes a placeholder, and a word group that includes a plurality of preset words for replacing the placeholder. The method includes: in response to receipt of a command for execution of the computer program product, displaying an editing interface including the main message template; in response to receipt of user operation of a selection of the main message template, displaying the template text; in response to receipt of user operation of a selection of one of the preset words via the user interface, generating an edited text by replacing the placeholder with the one of the preset words in the template text; and outputting the edited text as a message.
    Type: Application
    Filed: April 25, 2023
    Publication date: March 14, 2024
    Inventors: Yi-Ru CHIU, Ting-Yi LI, Hong-Xun WANG, Jin-Lin CHEN, Chih-Hsuan YEH, Chia-Chi YIN, Wei-Ting LI, Po-Lun CHANG
  • Publication number: 20240087877
    Abstract: A backside metallized compound semiconductor device includes a compound semiconductor wafer and a metal layered structure. The compound semiconductor wafer includes a substrate having opposite front and back surfaces, and a ground pad structure formed on the front surface. The substrate is formed with a via extending from the back surface to the front surface to expose a side wall of the substrate and a portion of the ground pad structure. The metal layered structure is disposed on the back surface, and covers the side wall and the portion of the ground pad structure. The metal layered structure includes an adhesion layer, a seed layer, a gold layer, and an electroplated copper layer that are formed on the back surface in such order. The method for manufacturing the backside metallized compound semiconductor device is also disclosed.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 14, 2024
    Inventors: Tsung-Te CHIU, Kechuang LIN, Houng-Chi WEI, Chia-Chu KUO, Bing-Han CHUANG
  • Publication number: 20240074147
    Abstract: A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a substrate, a bonding structure, a bit line, and a word line. The bonding structure is disposed on the substrate. The bit line is disposed on the bonding structure. The channel layer is disposed on the bit line. The word line surrounds the channel layer. The bonding structure includes a dielectric material.
    Type: Application
    Filed: June 26, 2023
    Publication date: February 29, 2024
    Inventors: YI-JEN LO, CHIANG-LIN SHIH, HSIH-YANG CHIU
  • Publication number: 20240074145
    Abstract: A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a substrate, a bonding structure, a bit line, and a word line. The bonding structure is disposed on the substrate. The bit line is disposed on the bonding structure. The channel layer is disposed on the bit line. The word line surrounds the channel layer. The bonding structure includes a dielectric material.
    Type: Application
    Filed: August 26, 2022
    Publication date: February 29, 2024
    Inventors: YI-JEN LO, CHIANG-LIN SHIH, HSIH-YANG CHIU
  • Patent number: 11917144
    Abstract: Various schemes for realizing efficient in-loop filtering are described, manifested in low latency and reduced hardware cost for an in-loop filter comprising at least two filtering stages. An apparatus receives pixel data of a current block of a picture and one or more neighboring blocks thereof, based on which the apparatus performs a filtering operation and generates a filtered block that includes completely filtered sub-blocks and partially filtered sub-blocks. The apparatus further outputs an output block that includes the completely filtered sub-blocks as well as a respective portion of each of the partially filtered sub-blocks, wherein the respective portion is adjacent to one of the completely filtered sub-blocks.
    Type: Grant
    Filed: June 19, 2022
    Date of Patent: February 27, 2024
    Assignee: MediaTek Inc.
    Inventors: Yueh-Lin Wu, Min-Hao Chiu, Yen-Chieh Huang
  • Publication number: 20240036680
    Abstract: An electronic device may have a display with touch sensors. One or more shielding layers may be interposed between the display and the touch sensors. The display may include transistors with gate conductors, a first planarization layer formed over the gate conductors, one or more contacts formed in a first source-drain layer within the first planarization layer, a second planarization layer formed on the first planarization layer, one or more data lines formed in a second source-drain layer within the second planarization layer, a third planarization layer formed on the second planarization layer, and a data line shielding structure formed at least partly in a third source-drain layer within the third planarization layer. The data line shielding structure may be a routing line, a blanket layer, a mesh layer formed in one or more metal layers, and/or a data line covering another data line.
    Type: Application
    Filed: May 25, 2023
    Publication date: February 1, 2024
    Inventors: Shinya Ono, Suhwan Moon, Dong-Gwang Ha, Jiaxi Hu, Hao-Lin Chiu, Kwang Soon Park, Hassan Edrees, Wen-I Hsieh, Jiun-Jye Chang, Chin-Wei Lin, Kyung Wook Kim
  • Patent number: 11828780
    Abstract: Systems and methods are described for reporting capacitance of a capacitor of a power backup circuit comprising a plurality of metal-oxide-semiconductor field-effect transistors (MOSFETs). The system may also include a bleeder resistor and a voltage detection circuit. When capacitance monitoring is active, a first MOSFET may be turned off, causing the capacitor to be discharged via the bleeder resistor. After predetermined time intervals, a first drain voltage and a second drain voltage of the first MOSFET may be determined using the voltage detection circuit. The drain voltage readings at the different times may be used to determine the capacitance of the capacitor, which may be used to generate and transmit a report on capacitor performance and status.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: November 28, 2023
    Assignee: ZT Group Int'l, Inc.
    Inventors: Yung-Tsung Hsieh, Chi-Lin Chiu
  • Publication number: 20230196521
    Abstract: The disclosure provides a test result recognizing method and a test result recognizing device. The method includes: controlling an image-capturing device to capture a first image of a display screen according to an image-capturing parameter; in response to determining that a reference image area including a first designated character string exists in the first image, controlling the image-capturing device to capture a first test image of the display screen according to the image-capturing parameter; extracting a first image area corresponding to the reference image area from the first test image, and performing a text dividing operation on the first image area to convert the first image area into a second image area; and performing a text recognition operation on the second image area to obtain a first test result corresponding to the first test image.
    Type: Application
    Filed: June 2, 2022
    Publication date: June 22, 2023
    Applicant: Acer Incorporated
    Inventors: Sheng-Lin Chiu, Cheng-Tse Wu, An-Cheng Lee, Wei-Ren Lin, Ying-Shih Hung
  • Publication number: 20230190411
    Abstract: Methods and apparatuses (including software) for optimizing dental treatment plans, including for optimizing the treatment plans using dental aligners. These methods and apparatuses may optimize a treatment plan by estimating a difference between a target set of tooth position and a predicted set of tooth positions using the treatment plan using a prediction network trained to use multiple translational and rotational directions for individual teeth as well as reaction forces on the individual teeth based on adjacent teeth.
    Type: Application
    Filed: December 16, 2022
    Publication date: June 22, 2023
    Inventors: Yi-Lin CHIU, Yuxiang WANG, Luyao CAI, Jun SATO, Iman SHOJAEI, Manlio Fabio VALDIVIESO CASIQUE, Minghao DAI, Xi CAI, Jeeyoung CHOI, Eric YAU
  • Patent number: 11580905
    Abstract: A display may include an array of pixels that receive control signals from a chain of gate drivers. Each gate driver may include a logic sub-circuit and an output buffer sub-circuit. The output buffer sub-circuit may include depletion mode semiconducting oxide transistors with high mobility. The logic sub-circuit may include semiconducting oxide transistors, some of which can be depletion mode transistors and some of which can be enhancement mode transistors with lower mobility. The logic sub-circuit may include at least a carry circuit, a voltage setting circuit, an inverting circuit, a discharge circuit.
    Type: Grant
    Filed: May 19, 2022
    Date of Patent: February 14, 2023
    Assignee: Apple Inc.
    Inventors: Rungrot Kitsomboonloha, Chin-Wei Lin, Shinya Ono, Gihoon Choo, Hao-Lin Chiu, Kyung Wook Kim, Pei-En Chang, Szu-Hsien Lee, Zino Lee
  • Patent number: D1027182
    Type: Grant
    Filed: August 15, 2022
    Date of Patent: May 14, 2024
    Assignees: Interface Technology (ChengDu) Co., Ltd., INTERFACE OPTOELECTRONICS (SHENZHEN) CO., LTD., GENERAL INTERFACE SOLUTION LIMITED
    Inventors: Chun-Ming Cheng, Chih-Lin Liao, Yi-Chia Chiu, Chun-Ta Chen, Po-Lun Chen