Patents by Inventor Lin Su
Lin Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145554Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure, the method includes forming a buffer layer over a substrate. An active layer is formed on the buffer layer. A top electrode is formed on the active layer. An etch process is performed on the buffer layer and the substrate to define a plurality of pillar structures. The plurality of pillar structures include a first pillar structure laterally offset from a second pillar structure. At least portions of the first and second pillar structures are spaced laterally between sidewalls of the top electrode.Type: ApplicationFiled: January 11, 2024Publication date: May 2, 2024Inventors: Yao-Chung Chang, Chun Lin Tsai, Ru-Yi Su, Wei Wang, Wei-Chen Yang
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Publication number: 20240143145Abstract: A method and apparatus for aiming at a virtual object in a virtual environment, which: displays a user interface (UI), the UI including a picture of a virtual environment including a first virtual object and at least one second virtual object located in the virtual environment; displays a dot aiming indicator in the virtual environment in response to an aiming instruction, the dot aiming indicator being used for indicating an aiming point selected by an aiming operation on a ground plane of the virtual environment; and controls the first virtual object to aim at a target virtual object, which is a virtual object selected from a second virtual object in a target selection range which is a selection range determined by using the aiming point as a benchmark.Type: ApplicationFiled: December 28, 2023Publication date: May 2, 2024Applicant: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITEDInventors: Yu Lin WAN, Jianmiao Weng, Xun Hu, Shan Dong Su, Yong Zhang
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Publication number: 20240124448Abstract: The invention provides a novel class of therapeutic agents that are safe and effective TYK2 inhibitors and pharmaceutical compositions of these compounds and methods of preparation and use thereof against various TYK2-mediated diseases and disorders.Type: ApplicationFiled: September 25, 2023Publication date: April 18, 2024Inventors: Zhaokui Wan, Michael Lawrence Vazquez, Gurmit Grewal, Xiaodong Li, Lin Su, Jingyu Wu
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Patent number: 11961912Abstract: The present application provides a semiconductor device and the method of making the same. The method includes recessing a fin extending from a substrate, forming a base epitaxial feature on the recessed fin, forming a bar-like epitaxial feature on the base epitaxial feature, and forming a conformal epitaxial feature on the bar-like epitaxial feature. The forming of the bar-like epitaxial feature includes in-situ doping the bar-like epitaxial feature with an n-type dopant at a first doping concentration. The forming of the conformal epitaxial feature includes in-situ doping the conformal epitaxial feature with a second doping concentration greater than the first doping concentration.Type: GrantFiled: June 6, 2022Date of Patent: April 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chun-An Lin, Wei-Yuan Lu, Feng-Cheng Yang, Tzu-Ching Lin, Li-Li Su
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Patent number: 11961834Abstract: A semiconductor device includes a first diode, a second diode, a clamp circuit and a third diode. The first diode is coupled between an input/output (I/O) pad and a first voltage terminal. The second diode is coupled with the first diode, the I/O pad and a second voltage terminal. The clamp circuit is coupled between the first voltage terminal and the second voltage terminal. The second diode and the clamp circuit are configured to direct a first part of an electrostatic discharge (ESD) current flowing between the I/O pad and the first voltage terminal. The third diode, coupled to the first voltage terminal, and the second diode include a first semiconductor structure configured to direct a second part of the ESD current flowing between the I/O pad and the first voltage terminal.Type: GrantFiled: March 21, 2022Date of Patent: April 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Po-Lin Peng, Li-Wei Chu, Ming-Fu Tsai, Jam-Wem Lee, Yu-Ti Su
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Publication number: 20240120735Abstract: An electrostatic discharge (ESD) circuit includes a first ESD detection circuit, a first discharging circuit and a first ESD assist circuit. The first ESD detection circuit is coupled between a first node having a first voltage and a second node having a second voltage. The first discharging circuit includes a first transistor. The first transistor has a first gate, a first drain, a first source and a first body terminal. The first gate is coupled to the first ESD detection circuit by a third node. The first drain is coupled to the first node. The first source and the first body terminal are coupled together at the second node. The first ESD assist circuit is coupled between the second and third node, and configured to clamp a third voltage of the third node at the second voltage during an ESD event at the first or second node.Type: ApplicationFiled: December 19, 2023Publication date: April 11, 2024Inventors: Chia-Lin HSU, Ming-Fu TSAI, Yu-Ti SU, Kuo-Ji CHEN
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Publication number: 20240110916Abstract: Disclosed herein is a method for identifying and treating an early-stage hepatocellular carcinoma (HCC) in a subject. The method mainly includes determining the level of serum amyloid A (SAA) protein, and providing anti-cancer treatment based on the determined level of SAA protein. According to some embodiments of the present disclosure, the anti-cancer treatment is provided when the determined level of SAA protein is lower than that of a first control sample, or when the determined level of SAA protein is higher than that of a second control sample. In some embodiments, the first control sample is derived from a subject having a late stage HCC, and the second control sample is derived from a subject having a liver disease that is any of hepatitis, liver cirrhosis, or a combination thereof.Type: ApplicationFiled: January 21, 2022Publication date: April 4, 2024Applicant: Academia SinicaInventors: Yun-Ru CHEN, Jin-Lin WU, Pei-Jer CHEN, Tung-Hung SU
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Publication number: 20240113099Abstract: An IC device includes first and second CMOS structures positioned in n-type doped regions of a substrate, the first CMOS structure including a common gate terminal, first NMOS body and source contacts, and first PMOS body and source contacts, the second CMOS structure including a common drain terminal, second NMOS body and source contacts, and second PMOS body and source contacts. The IC device includes a first electrical connection from the common drain terminal to the common gate terminal, a clamp device including a diode, a second electrical connection from a cathode of the diode to the first PMOS body and source contacts, and a third electrical connection from an anode of the of the diode to the first NMOS body and source contacts, and entireties of each of the second and third electrical connections are positioned between the substrate and a third metal layer of the IC device.Type: ApplicationFiled: April 28, 2023Publication date: April 4, 2024Inventors: Chia-Lin HSU, Yu-Ti SU
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Publication number: 20240097888Abstract: In a file sharing system, a key manager unit realizes a correspondence between the first user identifier and the first public key in response to a registration request of the first user, generates a first key material for encrypting the first file into a first encrypted file, and generates a first credential according to the first user identifier, the first file identifier, the first public key and the first key material after receiving an access-right claim request to the first file from the first user. A file storage unit stores the first encrypted file and the first credential. The first user uses the first user identifier, the first file identifier and the first private key to retrieve the first key material out of the first credential, and uses the first key material to decrypt the first encrypted file into the first file.Type: ApplicationFiled: September 18, 2023Publication date: March 21, 2024Inventors: CHIA-JUNG LIANG, CHIHHUNG LIN, CHIH-PING HSIAO, YU-JIE SU, CHIA-HSIN CHENG, TUN-HOU WANG, MENG-CHAO TSAI, YUEH-CHIN LIN
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Publication number: 20240082729Abstract: A virtual object control method and apparatus, a terminal, and a storage medium. The method includes: displaying a virtual scene interface, the virtual scene interface including a first virtual object, second virtual objects, and ability controls; determining, in response to a first trigger operation on a first ability control, a target virtual object from the second virtual objects and according to the first trigger operation, and controlling the first virtual object to cast a first ability on the target virtual object; determining the target virtual object as an ability casting target corresponding to a second ability when a second trigger operation on a second ability control meets an ability continuous casting condition, the second trigger operation being triggered during ability casting of the first ability; and controlling the first virtual object to cast the second ability on the target virtual object.Type: ApplicationFiled: November 20, 2023Publication date: March 14, 2024Applicant: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LTDInventors: Yu Lin WAN, Xun Hu, Shan Dong Su
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Publication number: 20240085803Abstract: Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.Type: ApplicationFiled: November 20, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tai-I Yang, Wei-Chen Chu, Hsiang-Wei Liu, Shau-Lin Shue, Li-Lin Su, Yung-Hsu Wu
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Publication number: 20240087962Abstract: A semiconductor structure and method for manufacturing thereof are provided. The semiconductor structure includes a silicon substrate having a first surface, a III-V layer on the first surface of the silicon substrate and over a first active region, and an isolation region in a portion of the III-V layer extended beyond the first active region. The first active region is in proximal to the first surface. The method includes the following operations. A silicon substrate having a first device region and a second device region is provided, a first active region is defined in the first device region, a III-V layer is formed on the silicon substrate, an isolation region is defined across a material interface in the III-V layer by an implantation operation, and an interconnect penetrating through the isolation region is formed.Type: ApplicationFiled: November 24, 2023Publication date: March 14, 2024Inventors: MAN-HO KWAN, FU-WEI YAO, RU-YI SU, CHUN LIN TSAI, ALEXANDER KALNITSKY
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Patent number: 11929363Abstract: In some embodiments, a semiconductor device is provided, including a first doped region of a first conductivity type configured as a first terminal of a first diode, a second doped region of a second conductivity type configured as a second terminal of the first diode, wherein the first and second doped regions are coupled to a first voltage terminal; a first well of the first conductivity type surrounding the first and second doped regions in a layout view; a third doped region of the first conductivity type configured as a first terminal, coupled to an input/output pad, of a second diode; and a second well of the second conductivity type surrounding the third doped region in the layout view. The second and third doped regions, the first well, and the second well are configured as a first electrostatic discharge path between the I/O pad and the first voltage terminal.Type: GrantFiled: March 21, 2022Date of Patent: March 12, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Po-Lin Peng, Li-Wei Chu, Ming-Fu Tsai, Jam-Wem Lee, Yu-Ti Su
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Patent number: 11923306Abstract: A method for manufacturing a semiconductor structure includes forming a plurality of dummy structures spaced apart from each other, forming a plurality of dielectric spacers laterally covering the dummy structures to form a plurality of trenches defined by the dielectric spacers, filling a conductive material into the trenches to form electrically conductive features, selectively depositing a capping material on the electrically conductive features to form a capping layer, removing the dummy structures to form a plurality of recesses defined by the dielectric spacers, filling a sacrificial material into the recesses so as to form sacrificial features, depositing a sustaining layer on the sacrificial features, and removing the sacrificial features to form air gaps confined by the sustaining layer and the dielectric spacers.Type: GrantFiled: August 30, 2021Date of Patent: March 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Wei Su, Chia-Tien Wu, Hsin-Ping Chen, Shau-Lin Shue
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Publication number: 20240074047Abstract: A conductive bump structure of a circuit board includes at least one composite conductive bump formed in at least one bump preservation region on a conductive layer of the circuit board. The composite conductive bump includes a raised portion and a conductive pillar. The raised portion is raised from a top surface of the conductive layer by a height. A bottom of the conductive pillar is in contact with and is combined with a curved top surface of the raised portion, and a top of the conductive pillar is raised upwards to protrude beyond the top planar surface of the conductive layer by a protrusion height.Type: ApplicationFiled: May 23, 2023Publication date: February 29, 2024Inventors: KUO-FU SU, CHIH-HENG CHUO, CLINTON LIN
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Patent number: 11911460Abstract: A lipid delivery system, a virus-like structure (VLS) vaccine constructed therefrom, and a lipid particle capable of encapsulating an mRNA molecule encoding a SARS-CoV-2-specific antigen are provided. After the lipid particle encapsulates an mRNA molecule encoding a SARS-CoV-2 antigen, a SARS-CoV-2 S1 antigen protein can be embedded on a surface of an envelope structure of the lipid under specific buffer conditions to produce a VLS vaccine with an antigen-encoding mRNA molecule encapsulated inside and an outer membrane presenting a required viral antigen protein. The vaccine has a superior specific antibody-inducing ability to a SARS-CoV-2 mRNA vaccine and a polypeptide vaccine, can maintain a long-lasting high antibody level, and can also exhibit excellent immune binding abilities for the emerging different variants.Type: GrantFiled: August 1, 2023Date of Patent: February 27, 2024Assignees: Weirui Biotechnology (Kunming) Co., LTD., Shandong Weigao Litong Biological Products Co., Ltd.Inventors: Qihan Li, Kaili Ma, Yanmei Li, Jingjing Zhang, Lichun Wang, Changyong Mu, Xiaowu Peng, Yanrui Su, Chang'e Liu, Liping He, Lin Feng, Dongxiu Gao, An Wang, Hongbing Li, Gang Xu, Fuyun He, Lichun Zheng, Hongkun Yi
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Patent number: 11860550Abstract: Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.Type: GrantFiled: July 19, 2022Date of Patent: January 2, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tai-I Yang, Wei-Chen Chu, Hsiang-Wei Liu, Shau-Lin Shue, Li-Lin Su, Yung-Hsu Wu
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Patent number: 11829781Abstract: A method of remotely modifying a basic input/output system (BIOS) configuration setting includes steps of: transmitting, by a remote computer, a modification instruction to a cloud server; transmitting, by the cloud server to a POS system, a new configuration value of the BIOS configuration setting contained in the modification instruction; determining, by an embedded controller of the POS system, whether the new configuration value is identical to an original configuration value of the BIOS configuration setting; and by the embedded controller when a result of the determination is negative, updating the BIOS configuration setting and transmitting a response instruction to the remote computer.Type: GrantFiled: October 6, 2021Date of Patent: November 28, 2023Assignee: FLYTECH TECHNOLOGY CO., LTD.Inventors: Li-Chun Chou, Shui-Chin Tsai, Ting-You Liou, Chien-Lin Su
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Publication number: 20230263813Abstract: Provided is a pharmaceutical composition including gastrodin and a use thereof for the prevention or the treatment of amyotrophic lateral sclerosis. The pharmaceutical composition is effective in reducing neuronal axon degeneration and neurofibromin accumulation, improving symptoms of amyotrophic lateral sclerosis and extending life of patients of amyotrophic lateral sclerosis.Type: ApplicationFiled: September 16, 2022Publication date: August 24, 2023Inventors: Chia-Yu CHANG, Shinn-Zong LIN, Hsiao-Chien TING, Hui-I YANG, Horng-Jyh HARN, Hong-Lin SU, Ching-Ann LIU, Yu-Shuan CHEN, Tzyy-Wen CHIOU, Tsung-Jung HO
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Patent number: D1002054Type: GrantFiled: September 19, 2022Date of Patent: October 17, 2023Inventor: Lin Su