Patents by Inventor Lin-Yin Wong
Lin-Yin Wong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7968991Abstract: A stacked package module is disclosed, which comprises: a first package structure comprising a first circuit board with a first chip embedded therein, wherein the first chip has a plurality of electrode pads; the first circuit board comprises a first surface, an opposite second surface, a plurality of exposed electro-connecting ends, a plurality of first conductive pads on the first surface, a plurality of conductive vias, and at least one circuit layer, therewith the electrode pads of the first chip electrically connecting to the electro-connecting ends and the first conductive pads directly through the conductive vias and the circuit layer; and a second package structure electrically connecting to the first package structure through a plurality of first solder balls to make a package on package. The stacked package module of this invention has characters of compact size, high performance, high flexibility, and detachability.Type: GrantFiled: October 25, 2007Date of Patent: June 28, 2011Assignee: Unimicron Technology Corp.Inventors: Lin-Yin Wong, Mao-Hua Yeh, Wang-Hsiang Tsai
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Patent number: 7880296Abstract: The present invention provides a chip carrier structure having a semiconductor chip embedded therein and a protective metal layer formed thereon and a fabrication method thereof. The chip carrier structure includes a chip-embedded carrier structure, and a metal layer formed by electroplating on the bottom surface and side surfaces of the chip-embedded carrier structure. The metal layer prevents moisture from crossing the side surfaces of the chip-embedded carrier structure, so as to prevent delamination, provide a shielding effect, and improve heat dissipation through the metal layer.Type: GrantFiled: March 7, 2008Date of Patent: February 1, 2011Assignee: Unimicron Technology Corp.Inventors: Lin-Yin Wong, Zao-Kuo Lai
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Patent number: 7656015Abstract: Provided is a packaging substrate with a heat-dissipating structure, including a core layer with a first surface and an opposite second surface having a first metal layer and a second metal layer respectively. Portions of the first metal layer are exposed from a second cavity penetrating the core layer and second metal layer. Portions of the second metal layer are exposed from a first cavity penetrating the core layer and first metal layer. Semiconductor chips each having an active surface with electrode pads thereon and an opposite inactive surface are received in the first and second cavities and attached to the second metal layer and the first metal layer respectively. Conductive vias disposed in build-up circuit structures electrically connect to the electrode pads of the semiconductor chips. A heat-dissipating through hole penetrating the core layer and build-up circuit structures connects the metal layers and contact pads.Type: GrantFiled: September 12, 2008Date of Patent: February 2, 2010Assignee: Phoenix Precision Technology CorporationInventors: Lin-Yin Wong, Mao-Hua Yeh
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Patent number: 7507915Abstract: A stack structure of carrier boards embedded with semiconductor components and a method for fabricating the same are proposed. A first carrier board and a second carrier board, each of which having at least one through hole, are provided. A first protecting layer and a second protecting layer are formed on a surface of the first and second carrier boards respectively. At least one first semiconductor component and at least one second semiconductor component are disposed on the first and second protecting layers and accommodated in the first and second through holes respectively. A dielectric layer is laminated between the surfaces of the first and second carrier boards without the protecting layers formed thereon. Thus, a modularized package structure with reduced space waste is formed.Type: GrantFiled: August 4, 2006Date of Patent: March 24, 2009Assignee: Phoenix Precision Technology CorporationInventors: Chia-Wei Chang, Lin-Yin Wong, Zao-Kuo Lai, Chung-Cheng Lien
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Publication number: 20090072384Abstract: Provided is a packaging substrate with a heat-dissipating structure, including a core layer with a first surface and an opposite second surface having a first metal layer and a second metal layer respectively. Portions of the first metal layer are exposed from a second cavity penetrating the core layer and second metal layer. Portions of the second metal layer are exposed from a first cavity penetrating the core layer and first metal layer. Semiconductor chips each having an active surface with electrode pads thereon and an opposite inactive surface are received in the first and second cavities and attached to the second metal layer and the first metal layer respectively. Conductive vias disposed in build-up circuit structures electrically connect to the electrode pads of the semiconductor chips. A heat-dissipating through hole penetrating the core layer and build-up circuit structures connects the metal layers and contact pads.Type: ApplicationFiled: September 12, 2008Publication date: March 19, 2009Applicant: Phoenix Precision Technology CorporationInventors: Lin-Yin Wong, Mao-Hua Yeh
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Publication number: 20080246135Abstract: A stacked package module is disclosed, which comprises: a first package structure comprising a first circuit board with a first chip embedded therein, wherein the first chip has a plurality of electrode pads; the first circuit board comprises a first surface, an opposite second surface, a plurality of exposed electro-connecting ends, a plurality of first conductive pads on the first surface, a plurality of conductive vias, and at least one circuit layer, therewith the electrode pads of the first chip electrically connecting to the electro-connecting ends and the first conductive pads directly through the conductive vias and the circuit layer; and a second package structure electrically connecting to the first package structure through a plurality of first solder balls to make a package on package. The stacked package module of this invention has characters of compact size, high performance, high flexibility, and detachability.Type: ApplicationFiled: October 25, 2007Publication date: October 9, 2008Applicant: Phoenix Precision Technology CorporationInventors: Lin-Yin Wong, Mao-Hua Yeh, Wang-Hsiang Tsai
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Publication number: 20080230886Abstract: A stacked package module is disclosed, which comprises: a first package structure comprising a first circuit board with a first chip embedded therein, wherein the first chip has a plurality of electrode pads, the first circuit board comprises a first surface, an opposite second surface, a plurality of first conductive pads on the first surface, a plurality of second conductive pads on the second surface, a plurality of conductive vias, and at least one circuit layer, and the electrodes of the first chip directly electrically connect to the conductive pads on the surfaces of the circuit board through the conductive vias and the circuit layer within the circuit board; and a second package structure electrically connecting to the first package structure through a plurality of solder balls to make package on package. The stacked package module provided by this invention has characteristics of compact size, high performance, and high flexibility.Type: ApplicationFiled: October 25, 2007Publication date: September 25, 2008Applicant: Phoenix Precision Technology CorporationInventors: Lin-Yin Wong, Mao-Hua Yeh, Wang-Hsiang Tsai
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Publication number: 20080217762Abstract: The present invention provides a chip carrier structure having a semiconductor chip embedded therein and a protective metal layer formed thereon and a fabrication method thereof. The chip carrier structure includes a chip-embedded carrier structure, and a metal layer formed by electroplating on the bottom surface and side surfaces of the chip-embedded carrier structure. The metal layer prevents moisture from crossing the side surfaces of the chip-embedded carrier structure, so as to prevent delamination, provide a shielding effect, and improve heat dissipation through the metal layer.Type: ApplicationFiled: March 7, 2008Publication date: September 11, 2008Applicant: PHOENIX PRECISION TECHNOLOGY CORPORATIONInventors: Lin-Yin Wong, Zao-Kuo Lai
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Patent number: 7396753Abstract: A semiconductor package substrate is provided having a plurality of bonding pads on at least one surface thereof and covered by a conductive film. A photoresist layer formed over the conductive film has a plurality of first openings for exposing portions of the conductive film corresponding to the bonding pads. The exposed portions of the conductive film is removed to expose the bonding pads respectively via the first openings. The exposed bonding pads are plated with a metal layer respectively. Then, the photoresist layer and the remainder of the conductive film covered by the photoresist layer are removed. A solder mask having a plurality of second openings may be formed on the surface of the substrate, and allows the plated metal layer on the bonding pads respectively to be exposed via the second openings.Type: GrantFiled: September 8, 2005Date of Patent: July 8, 2008Assignee: Phoenix Precision Technology CorporationInventors: Chih-Liang Chu, E-Tung Chou, Lin-Yin Wong
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Patent number: 7323762Abstract: A semiconductor package substrate with embedded resistors and a method for fabricating the same are proposed. Firstly, an inner circuit board having a first circuit layer thereon is provided, and a plurality of resistor electrodes are formed in the fist circuit layer. Then, a patterned resistive material is formed on the inner circuit board and electrically connected to the resistor electrodes to accurately define a resistance value of resistors. Subsequently, at least one insulating layer is coated on a surface of the circuit board having the patterned resistive material. At least one patterned second circuit layer is formed on the insulating layer and electrically connected to the resistor electrodes by a plurality of conductive vias formed in the insulating layer or plated through holes formed through the circuit board.Type: GrantFiled: November 1, 2004Date of Patent: January 29, 2008Assignee: Phoenix Precision Technology CorporationInventors: Zao-Kuo Lai, Lin-Yin Wong
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Publication number: 20070084628Abstract: A stack structure of carrier boards embedded with semiconductor components and a method for fabricating the same are proposed. A first carrier board and a second carrier board, each of which having at least one through hole, are provided. A first protecting layer and a second protecting layer are formed on a surface of the first and second carrier boards respectively. At least one first semiconductor component and at least one second semiconductor component are disposed on the first and second protecting layers and accommodated in the first and second through holes respectively. A dielectric layer is laminated between the surfaces of the first and second carrier boards without the protecting layers formed thereon. Thus, a modularized package structure with reduced space waste is formed.Type: ApplicationFiled: August 4, 2006Publication date: April 19, 2007Inventors: Chia-Wei Chang, Lin-Yin Wong, Zao-Kuo Lai, Chung-Cheng Lien
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Publication number: 20060261462Abstract: A semiconductor package substrate with embedded resistors and a method for fabricating the same are proposed. Firstly, an inner circuit board having a first circuit layer thereon is provided, and a plurality of resistor electrodes are formed in the fist circuit layer. Then, a patterned resistive material is formed on the inner circuit board and electrically connected to the resistor electrodes to accurately define a resistance value of resistors. Subsequently, at least one insulating layer is coated on a surface of the circuit board having the patterned resistive material. At least one patterned second circuit layer is formed on the insulating layer and electrically connected to the resistor electrodes by a plurality of conductive vias formed in the insulating layer or plated through holes formed through the circuit board.Type: ApplicationFiled: May 20, 2005Publication date: November 23, 2006Inventors: Zao-Kuo Lai, Lin-Yin Wong
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Patent number: 7135377Abstract: A semiconductor package substrate with embedded resistors and a method for fabricating the same are proposed. Firstly, an inner circuit board having a first circuit layer thereon is provided, and a plurality of resistor electrodes are formed in the fist circuit layer. Then, a patterned resistive material is formed on the inner circuit board and electrically connected to the resistor electrodes to accurately define a resistance value of resistors. Subsequently, at least one insulating layer is coated on a surface of the circuit board having the patterned resistive material. At least one patterned second circuit layer is formed on the insulating layer and electrically connected to the resistor electrodes by a plurality of conductive vias formed in the insulating layer or plated through holes formed through the circuit board.Type: GrantFiled: May 20, 2005Date of Patent: November 14, 2006Assignee: Phoenix Precision Technology CorporationInventors: Zao-Kuo Lai, Lin-Yin Wong
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Patent number: 7050304Abstract: A heat sink structure with embedded electronic components is proposed, wherein a plurality of recessed cavities are formed on a heat sink for embedding the electronic components and receiving at least one semiconductor chip therein. This arrangement enhances electric performance of a semiconductor package with the above heat sink structure and improves heat dissipating efficiency of the semiconductor package.Type: GrantFiled: February 3, 2004Date of Patent: May 23, 2006Assignee: Phoenix Precision Technology CorporationInventors: Shih-Ping Hsu, Lin-Yin Wong
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Publication number: 20060094156Abstract: A semiconductor package substrate with embedded resistors and a method for fabricating the same are proposed. Firstly, an inner circuit board having a first circuit layer thereon is provided, and a plurality of resistor electrodes are formed in the fist circuit layer. Then, a patterned resistive material is formed on the inner circuit board and electrically connected to the resistor electrodes to accurately define a resistance value of resistors. Subsequently, at least one insulating layer is coated on a surface of the circuit board having the patterned resistive material. At least one patterned second circuit layer is formed on the insulating layer and electrically connected to the resistor electrodes by a plurality of conductive vias formed in the insulating layer or plated through holes formed through the circuit board.Type: ApplicationFiled: November 1, 2004Publication date: May 4, 2006Inventors: Zao-Kuo Lai, Lin-Yin Wong
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Publication number: 20060006422Abstract: A semiconductor package substrate is provided having a plurality of bonding pads on at least one surface thereof and covered by a conductive film. A photoresist layer formed over the conductive film has a plurality of first openings for exposing portions of the conductive film corresponding to the bonding pads. The exposed portions of the conductive film is removed to expose the bonding pads respectively via the first openings. The exposed bonding pads are plated with a metal layer respectively. Then, the photoresist layer and the remainder of the conductive film covered by the photoresist layer are removed. A solder mask having a plurality of second openings may be formed on the surface of the substrate, and allows the plated metal layer on the bonding pads respectively to be exposed via the second openings.Type: ApplicationFiled: September 8, 2005Publication date: January 12, 2006Inventors: Chih-Liang Chu, E-Tung Chou, Lin-Yin Wong
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Publication number: 20050047094Abstract: A heat sink structure with embedded electronic components is proposed, wherein a plurality of recessed cavities are formed on a heat sink for embedding the electronic components and receiving at least one semiconductor chip therein. This arrangement enhances electric performance of a semiconductor package with the above heat sink structure and improves heat dissipating efficiency of the semiconductor package.Type: ApplicationFiled: February 3, 2004Publication date: March 3, 2005Inventors: Shih-Ping Hsu, Lin-Yin Wong
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Publication number: 20040099961Abstract: A semiconductor package substrate is provided having a plurality of bonding pads on at least one surface thereof and covered by a conductive film. A photoresist layer formed over the conductive film has a plurality of first openings for exposing portions of the conductive film corresponding to the bonding pads. The exposed portions of the conductive film is removed to expose the bonding pads respectively via the first openings. The exposed bonding pads are plated with a metal layer respectively. Then, the photoresist layer and the remainder of the conductive film covered by the photoresist layer are removed. A solder mask having a plurality of second openings may be formed on the surface of the substrate, and allows the plated metal layer on the bonding pads respectively to be exposed via the second openings.Type: ApplicationFiled: October 9, 2003Publication date: May 27, 2004Inventors: Chih-Liang Chu, E-Tung Chou, Lin-Yin Wong