Abstract: A circuit includes a memory cell column coupled to a bit line pair and a write circuit that alternately biases a first end of the bit lines toward power supply and reference voltage levels in a write operation. Each of first and second switching circuits at second ends of the bit lines includes first and second logic circuits, each including an input terminal coupled to a corresponding bit line, and first and second switching devices, each including a gate coupled to the corresponding logic circuit. The first logic circuit and switching device couple the corresponding bit line to a power supply node simultaneously with the write circuit biasing the corresponding bit line toward the power supply voltage level, and the second logic circuit and switching device couple the corresponding bit line to a reference node simultaneously with the write circuit biasing the corresponding bit line toward the reference voltage level.

Abstract: Systems, devices and methods for high-speed I/O margin testing can screen high volumes of pre-production and production parts and identify cases where the electrical characteristics have changed enough to impact operation. The margin tester disclosed is lower cost, easier to use and faster than traditional BERT and scopes and can operate on the full multi-lane I/O links in their standard operating states with full loading and cross-talk. The margin tester assesses the electrical receiver margin of an operation multi-lane high speed I/O link with a device under test simultaneously in either or both directions. In a technology-specific form, an embodiment of the margin tester can be implemented as an add-in card margin tester to test motherboard slots of a mother board under test, or as a as a motherboard with slots to test add-in cards.

Abstract: A map-based graphical user interface for a social media application displays to special social media activity information based on submission of geo-tagged social media items to the platform. For users and or submitted items that need predefined location fuzzing criteria, such activity is represented in the graphical user interface at an intentionally inaccurate position.

Abstract: Disclosed herein are related to an integrated circuit including a semiconductor layer. In one aspect, the semiconductor layer includes a first region, a second region, and a third region. The first region may include a circuit array, and the second region may include a set of interface circuits to operate the circuit array. A side of the first region may face a first side of the second region along a first direction. The third region may include a set of header circuits to provide power to the set of interface circuits through metal rails extending along a second direction. A side of the third region may face a second side of the second region along the second direction. In one aspect, the first side extending along the second direction is shorter than the second side extending along the first direction, and the metal rails are shorter than the first side.

Abstract: A test and measurement system has a test and measurement instrument having an adaptor with an interface configured to communicate through one or more communications links with a new device under test to receive new test results, a memory configured to store a database of test results and a database of analyzed test results related to tests performed with one or more prior devices under test, a data analyzer connected to the test and measurement instrument through the one or more communications link, the data analyzer configured to analyze the new test results based on the stored test results, and a health score generator configured to generate a health score for the new device under test based on the analysis from the data analyzer.

Abstract: A test and measurement system for analyzing a device under test, including a database configured to store test results related to tests performed with one or more prior devices under test, a receiver to receive new test results about a new device under test, a data analyzer configured to analyze the new test results based on the stored test results, and a health score generator configured to generate a health score for the new device under test based on the analysis from the data analyzer.

Abstract: Transistors with metal oxide channel material and a multi-composition gate dielectric. A surface of a metal oxide gate dielectric may be nitrided before deposition of a metal oxide channel material, for example to reduce gate capacitance of a TFT. Breakdown voltage and/or drive current of a TFT can be increased through the introduction of an additional metal oxide and/or nitride between the gate electrode and a metal oxide gate dielectric. The introduction of an intervening layer between two layers of a metal oxide gate dielectric can also increase breakdown voltage and/or drive current of a TFT.

Abstract: A margin tester including an identification reader configured to receive an adaptor identifier of an adaptor, an interface configured to connect to a device under test through the adaptor, and one or more processors configured to assess a margin, such as an electrical margin or an optical margin, of a device under test and tag the assessment with the adaptor identifier. Assessing the margin can include assessing the margin based on an expected margin that is predicted or provided based on the adaptor identifier.

Abstract: A cable structured to be repeatedly connected to a device, each repeated connection causing degradation of the cable, the cable including a condition indicator disposed on the cable and configured to be updated with each successive connection of the cable into the device.

Abstract: A calibrated test and measurement cable for connecting one or more devices under test and a test and measurement instrument, including a first port structured to electrically connect to a first signal lane, a second port structured to electrically connect to a second signal lane, a third port structured to electrically connect to a test and measurement instrument, and a multiplexer configured to switch between electrically connecting the first port to the third port and connected the second port to the third port. The first and second signal lanes can be included on the same device under test or different devices under test. An input can receive instructions to operate the multiplexer.

Abstract: A test and measurement system for analyzing a device under test, including a database configured to store test results related to tests performed with one or more prior devices under test, a receiver to receive new test results about a new device under test, a data analyzer configured to analyze the new test results based on the stored test results, and a health score generator configured to generate a health score for the new device under test based on the analysis from the data analyzer.

Abstract: Systems, devices and methods for high-speed I/O margin testing can screen high volumes of pre-production and production parts and identify cases where the electrical characteristics have changed enough to impact operation. The margin tester disclosed is lower cost, easier to use and faster than traditional BERT and scopes and can operate on the full multi-lane I/O links in their standard operating states with full loading and cross-talk. The margin tester assesses the electrical receiver margin of an operation multi-lane high speed I/O link with a device under test simultaneously in either or both directions. In a technology-specific form, an embodiment of the margin tester can be implemented as an add-in card margin tester to test motherboard slots of a mother board under test, or as a as a motherboard with slots to test add-in cards.

Abstract: Systems and methods for automated recognition of a device under test and retrieving data associated with the device under test based on the recognition. The systems and methods include receiving a recognition key based on an identifying characteristic of the device under test, matching the received recognition key to a stored key in a database, retrieving data related to the stored key when the received recognition key matches the stored key, transmitting instructions to perform an action on a test and measurement device based on the retrieved data, receiving new data related to the device under test, and updating the data in the database related to the stored key with the new data.

Abstract: The apparatus and method thereof for harmlessly and continuously measuring and recording a target protein expression and a number of growing cells are provided. By causing an AC current to flow through an electrode where cells grows thereon, the target protein expression and the number of growing cells are obtained via converting the impedance values of the electrode.

Abstract: An electronic apparatus with an antenna, an anti-jamming system and a method are disclosed. The electronic apparatus comprises a casing and the antenna. The antenna is composed of a patterned metal thin film and a carrier and provided for processing a wireless signal. The casing and the antenna are made by injection molding. When the electronic apparatus has a display device, the anti-jamming system can modulate a clock signal generated by the display device to prevent the multiplication of clock signal from interfering with signals within an operating band of the antenna.

Abstract: The preferred embodiment of the present invention presents a method and a device for a host control unit to communicate over a protocol compliant bus via the introduction of an auxiliary command control unit that handles communications to and from the protocol compliant bus. The auxiliary command control unit converts the high level commands of the host control unit to low-level protocol compliant electrical signals for transmission across the bus and further converts low-level protocol compliant electrical signals received from the bus into high level commands for use by the host processor.

Abstract: A storage container for an appendage of a compact disc comprises: a foldable board; a tray bonded to the foldable board, a recess formed on the tray, and a receiving cavity form at a bottom of the recess, at a bottom surface of the receiving cavity being formed a retaining structure for retaining compact disc; wherein a plurality of positioning portions are provided around peripheral sidewall of the recess, and a space is defined between the each of the positioning portions and the bottom surface of the recess, so that a appendage is received in the recess and are confined in the space by the positioning portions.

Abstract: A unitary wiper for a printhead on a print cartridge in an ink-jet printer is disclosed. The wiper is made of an elastomeric material and includes a base mounted in the ink-jet printer, a beam having a pair of approximately opposed substantially planar surfaces each of which terminates in a first wiping edge at a first end of the beam and at the base at a second end of the beam, and a slot formed on the beam, and extending along the second end from a third end of the beam to a fourth end of the beam. The first end is a plane surface and the beam further has at the plane surface a second wiping edge opposed to the first wiping edge.

Abstract: A method of fabricating local interconnects of polycide has been achieved. A substrate is provided. Narrowly spaced features, such as MOS transistor gates and polysilicon traces, are provided overlying the substrate. A dielectric layer is deposited overlying the substrate and the narrowly spaced features. The dielectric layer is patterned to form openings between the narrowly spaced features for planned contacts to the surface of the substrate. A doped polysilicon layer is deposited overlying the dielectric layer and filling the openings. The doped polysilicon layer is etched down to the top surface of the narrowly spaced features. The doped polysilicon layer remains in the spaces between the narrowly spaced features. A polycide layer is formed overlying the narrowly spaced features and the doped polysilicon layer. The polycide layer and the doped polysilicon layer are patterned to complete the contacts and create the local interconnects of polycide, and the integrated circuit device is completed.