Abstract: A transmission system includes a sending apparatus and N signal channels, where N?2, and N is an integer. The sending apparatus includes a first apparatus, and the first apparatus is configured to: obtain N to-be-transmitted signals and an encoding coefficient group, where the N to-be-transmitted signals are represented as an N×1 signal matrix X, and the encoding coefficient group is represented as an N×N orthogonal encoding matrix T; process the N to-be-transmitted signals based on the encoding coefficient group to generate N encoded first signals, where the N encoded first signals are represented as a signal matrix Y; and send the N encoded first signals to the N signal channels, where a signal on each signal channel corresponds to an element in a row of the signal matrix Y.

Abstract: Embodiments of this application provide a balance-unbalance conversion apparatus. The apparatus includes an insulation substrate, a first microstrip, a second microstrip, and a conductive ground. The first microstrip includes a first balance signal connection section, a first impedance matching section, and an unbalance signal connecting section. The unbalance signal connecting section is configured to transmit an unbalance signal. The second microstrip includes a second balance signal connecting section, a second impedance matching section, and a ground section. The second balance signal connecting section is configured to transmit a second component of the balance signal. The ground section is configured to connect to a ground signal. The first microstrip, the second microstrip, and the conductive ground are all disposed on the insulation substrate, and a cross-sectional area of at least a part of the first microstrip and/or at least a part of the second microstrip is gradient.

Abstract: A method, including obtaining a first protocol descriptor according to a protocol header field of an input packet, and further according to a preset protocol field mapping relationship, where the first protocol descriptor corresponds to the protocol header field of the input packet, and where the preset protocol field mapping relationship comprises a mapping relationship between the first protocol descriptor and the protocol field of the input packet, obtaining a second protocol descriptor according to the first protocol descriptor, obtaining, according to the preset protocol field mapping relationship and the second protocol descriptor, a second protocol header field, and obtaining an output packet, where the output packet comprises the second protocol header field.

Abstract: A method, including obtaining a first protocol descriptor according to a protocol header field of an input packet, and further according to a preset protocol field mapping relationship, where the first protocol descriptor corresponds to the protocol header field of the input packet, and where the preset protocol field mapping relationship comprises a mapping relationship between the first protocol descriptor and the protocol field of the input packet, obtaining a second protocol descriptor according to the first protocol descriptor, obtaining, according to the preset protocol field mapping relationship and the second protocol descriptor, a second protocol header field, and obtaining an output packet, where the output packet comprises the second protocol header field.

Abstract: This application relates to the field of storage technologies and discloses a content addressable memory, a data processing method, and a network device, to resolve a problem that an existing CAM has a relatively large area, and consumes relatively large power. The CAM includes bit units of M rows and N columns, each bit unit includes a first FeFET and a second FeFET, a source of the first FeFET is connected to a drain of the second FeFET, a source of the second FeFET is grounded, bit cells of a same column correspond to a same match line, and a drain of a first FeFET in each bit cell of a same column is connected to a match line corresponding to the column. Bit cells of a same row correspond to a same first bit line and a same second bit line, a gate of a first FeFET in each bit cell of a same row is connected to a first bit line corresponding to the row, and a gate of a second FeFET in each bit cell of a same row is connected to a second bit line corresponding to the row.

Abstract: This application discloses an optical backplane system, which includes a first upper-level optical interconnection module, a first lower-level optical interconnection module, and a second lower-level optical interconnection module. The first upper-level optical interconnection module includes M1 first interfaces and N1 second interfaces in connection relationships. The first lower-level optical interconnection module includes L1 third interfaces and K1 fourth interfaces in connection relationships. The second lower-level optical interconnection module includes L2 third interfaces and K2 fourth interfaces in connection relationships. The first upper-level optical interconnection module is connected to one of the L1 third interfaces of the first lower-level optical interconnection module by using one of the N1 second interfaces.

Abstract: This application provides a data transmission method and a network device. The method includes: sending, by a first network device, request information to a second network device; receiving, by the first network device, grant information sent by the second network device, where the grant information includes a first sequence number; determining, by the first network device, a first credit limit based on the first sequence number, where the first credit limit is an amount of data that is allowed to be sent by the first network device in a packet-distributed load sharing manner; and sending, by the first network device, data to the second network device based on the first credit limit.

Abstract: Embodiments of this application provide a balance-unbalance conversion apparatus. The apparatus includes an insulation substrate, a first microstrip, a second microstrip, and a conductive ground. The first microstrip includes a first balance signal connection section, a first impedance matching section, and an unbalance signal connecting section. The unbalance signal connecting section is configured to transmit an unbalance signal. The second microstrip includes a second balance signal connecting section, a second impedance matching section, and a ground section. The second balance signal connecting section is configured to transmit a second component of the balance signal. The ground section is configured to connect to a ground signal. The first microstrip, the second microstrip, and the conductive ground are all disposed on the insulation substrate, and a cross-sectional area of at least a part of the first microstrip and/or at least a part of the second microstrip is gradient.

Abstract: This application relates to the field of storage technologies and discloses a content addressable memory, a data processing method, and a network device, to resolve a problem that an existing CAM has a relatively large area, and consumes relatively large power. The CAM includes bit units of M rows and N columns, each bit unit includes a first FeFET and a second FeFET, a source of the first FeFET is connected to a drain of the second FeFET, a source of the second FeFET is grounded, bit cells of a same column correspond to a same match line, and a drain of a first FeFET in each bit cell of a same column is connected to a match line corresponding to the column. Bit cells of a same row correspond to a same first bit line and a same second bit line, a gate of a first FeFET in each bit cell of a same row is connected to a first bit line corresponding to the row, and a gate of a second FeFET in each bit cell of a same row is connected to a second bit line corresponding to the row.

Abstract: A method, including obtaining a first protocol descriptor according to a protocol header field of an input packet, and further according to a preset protocol field mapping relationship, where the first protocol descriptor corresponds to the protocol header field of the input packet, and where the preset protocol field mapping relationship comprises a mapping relationship between the first protocol descriptor and the protocol field of the input packet, obtaining a second protocol descriptor according to the first protocol descriptor, obtaining, according to the preset protocol field mapping relationship and the second protocol descriptor, a second protocol header field, and obtaining an output packet, where the output packet comprises the second protocol header field.

Abstract: A method, including obtaining a first protocol descriptor according to a protocol header field of an input packet, and further according to a preset protocol field mapping relationship, where the first protocol descriptor corresponds to the protocol header field of the input packet, and where the preset protocol field mapping relationship comprises a mapping relationship between the first protocol descriptor and the protocol field of the input packet, obtaining a second protocol descriptor according to the first protocol descriptor, obtaining, according to the preset protocol field mapping relationship and the second protocol descriptor, a second protocol header field, and obtaining an output packet, where the output packet comprises the second protocol header field.

Abstract: The present disclosure relates to registration methods and devices. One example method includes obtaining, by a line card, line card information of the line card, the line card comprising a fabric interface chip optically interconnected to a switch fabric chip in at least one switch fabric card by using an optical fiber, and sending, by the line card, the line card information to the at least one switch fabric card through an optical interconnect path. The at least one switch fabric card registers the line card based on the line card information.

Abstract: This application discloses an optical backplane system, which includes a first upper-level optical interconnection module, a first lower-level optical interconnection module, and a second lower-level optical interconnection module. The first upper-level optical interconnection module includes M1 first interfaces and N1 second interfaces in connection relationships. The first lower-level optical interconnection module includes L1 third interfaces and K1 fourth interfaces in connection relationships. The second lower-level optical interconnection module includes L2 third interfaces and K2 fourth interfaces in connection relationships. The first upper-level optical interconnection module is connected to one of the L1 third interfaces of the first lower-level optical interconnection module by using one of the N1 second interfaces.

Abstract: The present disclosure relates to registration methods and devices. One example method includes obtaining, by a line card, line card information of the line card, the line card comprising a fabric interface chip optically interconnected to a switch fabric chip in at least one switch fabric card by using an optical fiber, and sending, by the line card, the line card information to the at least one switch fabric card through an optical interconnect path. The at least one switch fabric card registers the line card based on the line card information.

Abstract: A data processing method and a related device are provided. The method includes receiving, by the ith processing circuit in a first circuit set, a first packet header and data D(1, i?1), obtaining data D?(1, i) based on a first field in the first packet header, and sending the first packet header and data D(1, i) to the (i+1)th processing circuit in the first circuit set, where the data D(1, i) is obtained based on the data D(1, i?1) and the data D?(1, i). The method also includes sending, by the ith processing circuit in the first circuit set, the data D(1, i) to the (i+1)th processing circuit in a second circuit set and sending, by the ith processing circuit in the second circuit set, a second packet header to the (i+1)th processing circuit in the second circuit set.

Abstract: A method, including obtaining a first protocol descriptor according to a protocol header field of an input packet, and further according to a preset protocol field mapping relationship, where the first protocol descriptor corresponds to the protocol header field of the input packet, and where the preset protocol field mapping relationship comprises a mapping relationship between the first protocol descriptor and the protocol field of the input packet, obtaining a second protocol descriptor according to the first protocol descriptor, obtaining, according to the preset protocol field mapping relationship and the second protocol descriptor, a second protocol header field, and obtaining an output packet, where the output packet comprises the second protocol header field.

Abstract: A packet edit processing method and a device are provided. In an embodiment, the method includes: generating an input packet template based on N to-be-edited protocol header fields of an input packet, and a preset protocol field mapping relationship, where the input packet template includes N protocol descriptors, and the protocol field mapping relationship is a mapping relationship between a protocol field included in a protocol descriptor and a protocol field included in a protocol header field; performing edit processing on the input packet template to obtain an output packet template; and converting, based on the preset protocol field mapping relationship, M protocol descriptors into M protocol header fields of an output packet, and replacing the N protocol header fields in the input packet with the M protocol header fields to obtain the output packet.

Abstract: Disclosed are a data processing method, a processor, and a data processing device. The method comprises: an arbiter sends data D(a,1) to a first processing circuit; the first processing circuit processes the data D(a,1) to obtain data D(1,2), the first processing circuit being a processing circuit among m processing circuits; the first processing circuit sends the data D(1,2) to a second processing circuit; the second processing circuit to an mth processing circuit separately process the received data; and the arbiter receives data D(m,a) sent by the mth processing circuit. The processor comprises an arbiter and a first processing circuit to an (m+1)th processing circuit. Each processing circuit in the first processing circuit to the (m+1)th processing circuit can receive first data to be processed sent by the arbiter, and process the first data to be processed. The scheme is helpful to improve efficiency of data processing.

Abstract: A method for determining instruction sequences, a related device, and a system. A method for determining instruction sequences may include: acquiring a function identifier; and determining M1 instruction sequences used to implement a function identified by the function identifier, where each instruction sequence in the M1 instruction sequences includes a unique entry instruction, and each instruction sequence in the M1 instruction sequences includes a unique exit instruction, where M1 is a positive integer, and the M1 instruction sequences are instruction sequences for creating a network packet processing program used to process a network packet. Solutions of embodiments of the present disclosure are advantageous for improving an extent of matching between a packet forwarding device and an instruction sequence that is executed by the packet forwarding device and used to process a network packet, and reducing an amount of invalid code run by the packet forwarding device.

Abstract: A data processing method and a related device are provided. The method includes receiving, by the ith processing circuit in a first circuit set, a first packet header and data D(1, i?1), obtaining data D?(1, i) based on a first field in the first packet header, and sending the first packet header and data D(1, i) to the (i+1)th processing circuit in the first circuit set, where the data D(1, i) is obtained based on the data D(1, i?1) and the data D?(1, i). The method also includes sending, by the ith processing circuit in the first circuit set, the data D(1, i) to the (i+1)th processing circuit in a second circuit set and sending, by the ith processing circuit in the second circuit set, a second packet header to the (i+1)th processing circuit in the second circuit set.