Abstract: A method and arrangement for a dma transfer mode having multiple transactions is provided. The invention generates a set of transaction entries for a DMA transfer each of which contains information related to the address and command instruction of a transaction. The transaction entries are stored in an address/cmd-output-FIFO. The invention negotiates for the control of the system bus. Upon gaining control of the bus, the commands and address relate to each transaction are sequentially place on the system bus. If the transaction is a read operation, data received back from the system bus is first stored in a data-in-FIFO before being sent to the desired destination. If the transaction is a write operation, the data to be transferred is first stored in a data-out-FIFO before being timely place on the system bus for transferring to the desired destination. In either case, the number of data words transferred is monitored to determine when a transaction is complete.

Abstract: A memory system that includes a memory controller and memory modules that provide address and control signals to groups of memory components through multiple busses. In one embodiment, each memory module is coupled to an address/control buss. The use of multiple address/control busses provides the necessary bandwidth so as to allow for fast access and control of memory components. Memory components are grouped into banks of memory components with each bank including three memory components. Memory modules are configured with one, two, four, or more banks of memory components on a given memory module. In one embodiment, the memory system includes six 48-bit memory modules that use SDRAM memory components. The six memory modules are used in a set to form a 288-bit memory word. When 16 Mbit or 64 Mbit memory components are used, this configuration gives a range of memory configurations from 32 megabytes to 2 gigabytes.

Abstract: A memory system that includes a memory controller and memory modules that provide address and control signals to groups of memory components through multiple busses. In one embodiment, each memory module is coupled to an address/control buss. The use of multiple address/control busses provides the necessary bandwidth so as to allow for fast access and control of memory components. Memory components are grouped into banks of memory components with each bank including three memory components. Memory modules are configured with one, two, four, or more banks of memory components on a given memory module. In one embodiment, the memory system includes six 48-bit memory modules that use SDRAM memory components. The six memory modules are used in a set to form a 288-bit memory word. When 16 Mbit or 64 Mbit memory components are used, this configuration gives a range of memory configurations from 32 megabytes to 2 gigabytes.