Abstract: The present invention is a method to increase yield and performance (speed and power dissipation) of ICs. It involves identifying gates in a layout by location and classification (orientation and neighboring features), and applying mask correction to the gates based on these features, together with the location of the chip in the optical field. Mask correction is applied to each chip having a unique position within the optical field separately. Mask correction involves increasing or decreasing the line widths in the layout of the gate layer of those lines corresponding to transistor gates, depending on a spatial and category-based correction scheme. The present invention further includes a set of methods to determine the mask correction amounts, given limits in mask correction resolution, based on the spatial CD maps for each of the gate categories.

Abstract: The present invention is a device to measure the deterministic structure of the variation of the gate critical dimension (CD), so that accurate topological information about CD variation within the optical field is obtained. The present invention also involves determining the most frequent gate configurations (orientation and neighboring features) in a layout of a specific circuit design, and including these most frequent gate configurations in the measurement device. The present invention further includes a method to determine CD maps across the optical field, based on the collection of CD data for specific gate configurations. The CD maps are used in the course of computer-aided design of IC's to improve the accuracy in which circuit performance metrics and yield are estimated. The present invention describes a set of methods in which the CD maps are integrated into the computer-aided design of ICs.