Patents by Inventor Ling-I CHENG

Ling-I CHENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240144531
    Abstract: In one example in accordance with the present disclosure, a mobile device is described. The example mobile device includes an image sensor to capture an image frame. The example mobile device also includes a processor for performing simultaneous localization and mapping (SLAM). The example mobile device further includes a memory communicatively coupled to the processor and storing executable instructions that when executed cause the processor to: (1) determine a current location of the mobile device in a local map based on features extracted from the image frame; (2) perform a panoramic check to determine whether a threshold number of keyframes surrounding the current location have been captured; and (3) determine whether to add the image frame to a keyframe database for local mapping based on the panoramic check.
    Type: Application
    Filed: October 27, 2022
    Publication date: May 2, 2024
    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Yow-Wei CHENG, Ling-I Hung
  • Patent number: 11757450
    Abstract: A true random-number generator generating a random variable is provided. A first delay circuit delays an input signal to generate a first delayed signal. A second delay circuit delays the first delayed signal to generate a second delayed signal. A first sampling circuit samples the input signal according to a clock signal to generate a first sampled signal. A second sampling circuit samples the first delayed signal according to the clock signal to generate a second sampled signal. A third sampling circuit samples the second delayed signal according to the clock signal to generate a third sampled signal. An operational circuit generates the random variable and adjusts a count value according to the first sampled signal, the second sampled signal, and the third sampled signal. The operational circuit adjusts the clock signal according to the count value.
    Type: Grant
    Filed: January 12, 2022
    Date of Patent: September 12, 2023
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventors: Ling-I Cheng, Chih-Ming Hsieh
  • Patent number: 11531058
    Abstract: A detection circuit is provided in the invention. The detection circuit includes a synchronous circuit, a comparison circuit and a fail-signal generating circuit. The comparison circuit is coupled to the synchronous circuit. The comparison circuit compares a target signal with a reference signal to generate a comparison result. The frequency of the reference signal is lower than the frequency of the target signal. The fail-signal generates circuit is coupled to the synchronous circuit and the comparison circuit. The fail-signal receives the comparison circuit. According to the comparison circuit, the fail-signal determines whether the target signal has failed.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: December 20, 2022
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventors: Ling-I Cheng, Yuan-Po Cheng, Pao-Shu Chang
  • Publication number: 20220311443
    Abstract: A true random-number generator generating a random variable is provided. A first delay circuit delays an input signal to generate a first delayed signal. A second delay circuit delays the first delayed signal to generate a second delayed signal. A first sampling circuit samples the input signal according to a clock signal to generate a first sampled signal. A second sampling circuit samples the first delayed signal according to the clock signal to generate a second sampled signal. A third sampling circuit samples the second delayed signal according to the clock signal to generate a third sampled signal. An operational circuit generates the random variable and adjusts a count value according to the first sampled signal, the second sampled signal, and the third sampled signal. The operational circuit adjusts the clock signal according to the count value.
    Type: Application
    Filed: January 12, 2022
    Publication date: September 29, 2022
    Inventors: Ling-I CHENG, Chih-Ming HSIEH
  • Publication number: 20210190852
    Abstract: A detection circuit is provided in the invention. The detection circuit includes a synchronous circuit, a comparison circuit and a fail-signal generating circuit. The comparison circuit is coupled to the synchronous circuit. The comparison circuit compares a target signal with a reference signal to generate a comparison result. The frequency of the reference signal is lower than the frequency of the target signal. The fail-signal generates circuit is coupled to the synchronous circuit and the comparison circuit. The fail-signal receives the comparison circuit. According to the comparison circuit, the fail-signal determines whether the target signal has failed.
    Type: Application
    Filed: September 2, 2020
    Publication date: June 24, 2021
    Inventors: Ling-I CHENG, Yuan-Po CHENG, Pao-Shu CHANG