Abstract: The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a first chip and a second chip. A first conductive connection wire of the first chip is connected to a first conductive contact pad, and a second conductive connection wire of the second chip is connected to a second conductive contact pad. In addition, the first conductive contact pad includes a first conductor group and a second conductor group, and the second conductive contact pad includes a third conductor group and a fourth conductor group.

Abstract: A semiconductor structure includes: a first substrate, with a first opening being provided on a surface of first substrate; and a first bonding structure positioned in the first opening. The first bonding structure includes a first metal layer and a second metal layer with a melting point lower than that of the first metal layer. The first metal layer includes a first surface in contact with a bottom surface of the first opening and a second surface opposite to the first surface, the second surface is provided with a first groove, an area, not occupied by the first metal layer and the first groove, of the first opening constitutes a second groove, the second metal layer is formed in the first groove and the second groove, and a surface, exposed from the second groove, of the second metal layer constitutes a bonding surface of the first bonding structure.

Abstract: Embodiments provide a semiconductor structure and a fabricating method. The semiconductor structure includes: a substrate having a power supply port; a memory module positioned on an upper surface of the substrate, where the memory module includes memory chips stacked in a first direction, the first direction is parallel to the upper surface of the substrate, each of the memory chips has a power supply signal line, at least one of the memory chips has a power supply wiring layer, the power supply signal line is electrically connected to the power supply wiring layer, the power supply wiring layer is positioned in the memory module, an end surface of the power supply wiring layer far away from the substrate is exposed by the memory module, and a solder bump is further provided on the end surface; and a lead frame electrically connected to the solder bump and the power supply port.

Abstract: A semiconductor structure, a method for manufacturing a semiconductor structure and a semiconductor device are provided. The semiconductor structure comprises: a logic die provided with a first wireless communication component; a plurality of memory components arrayed in a first direction and stacked on an upper surface of the logic die, the first direction being parallel to the upper surface of the logic die; and a first adhesive film arranged between any two adjacent memory components of the plurality of memory components and adhered to the any two adjacent memory components. Each of the plurality of memory components includes a plurality of memory dies arrayed in the first direction. Each of the plurality of memory dies is provided with a second wireless communication component. The second wireless communication component is in wireless communication with the first wireless communication component.

Abstract: Provided are a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a base having power ports, a memory module located on the base and including a plurality of memory dies stacked along a first direction, in which each of the memory dies has power-supply signal wires, at least one of the memory dies has a power-supply distribution layer, the power-supply signal wires are electrically connected with the power-supply distribution layer, the power-supply distribution layer includes a first distribution layer and a second distribution layer connected with each other, a plane of the first distribution layer is perpendicular to an upper surface of the base, the second distribution layer is located on a surface of the memory die away from the base; wire bonds connected with the second distribution layer; at least one lead frame connected with the wire bonds and the power ports.

Abstract: A semiconductor package structure and a manufacturing method thereof are provided. The semiconductor package structure includes a first semiconductor die and a second semiconductor die stack structure. A first wireless communication portion is formed in the first semiconductor die. The second semiconductor die stack structure includes a first die stack structure and a second die stack structure. A second wireless communication portion and a third wireless communication portion are respectively formed in two sides, along a second direction, of the first die stack structure. A fourth wireless communication portion is formed in one side, opposite to the first die stack structure, of the second die stack structure. The first direction is a direction parallel to a plane of the first semiconductor die, and the second direction is a direction perpendicular to the plane of the first semiconductor die.

Abstract: Provided are semiconductor package structure and a method for manufacturing the same. The semiconductor package structure includes: a first base; a first semiconductor chip connected to the first base; a second semiconductor chip stack structure located on the first semiconductor chip, the second semiconductor chip stack structure including a plurality of second semiconductor chips stacked in sequence in a first direction, the second semiconductor chip stack structure being provided with a plurality of first leads on an outermost side of the second semiconductor chips in the first direction, in which the first direction is a direction parallel to a plane of the first base; and at least one second base, signal lines in the at least one second base being connected to the first leads, the at least one second base being connected to the first base in a direction perpendicular to the plane of the first base.

Abstract: A semiconductor structure and semiconductor device are provided. The semiconductor structure includes a plurality of layers of memory modules stacked on an upper surface of the logic chip in a first direction which is perpendicular to the upper surface of the logic chip. Each storage module includes a plurality of memory chips stacked in a second direction which is parallel to the upper surface. Each memory chip in a top layer includes one second wireless communication part; and each memory chip in a non-top layer includes two second wireless communication parts arranged in the first direction and a wired communication part connected between the two second wireless communication parts. Two adjacent second wireless communication parts located on different memory chips in the first direction communicate with each other wirelessly; and each first wireless communication part communicates wirelessly with a closest second wireless communication part in a bottom memory chip.

Abstract: A semiconductor package structure includes: a first substrate; a first semiconductor die connected to the first substrate; a second semiconductor die stack structure located on the first semiconductor die, the second semiconductor die stack structure includes a plurality of second semiconductor dies sequentially stacked onto one another in a first direction, a plurality of second conductive bumps being formed on a side of the second semiconductor die stack structure in the first direction, in which the first direction is a direction parallel to a plane where the first substrate is located; and a second substrate, a signal line in the second substrate being connected to the plurality of second conductive bumps, the second substrate being connected to the first substrate in a direction perpendicular to the plane where the first substrate is located.

Abstract: A semiconductor structure, a method for manufacturing same, and a semiconductor device are provided. The semiconductor structure includes: a substrate having a groove and power supply pins; a storage module located in the groove; in which the storage module includes a plurality of storage chips stacked in a first direction, the first direction being parallel to the bottom surface of the groove; power supply signal lines being provided in each of the storage chips, and at least one of the plurality of storage chips having a power supply wiring layer electrically connected to the power supply signal lines; and conductive parts connected with the power supply wiring layer and the power supply pins.

Abstract: A semiconductor package structure includes: a first base plate; a first semiconductor chip connected to the first base plate; a second semiconductor chip stacking structure including at least one first chip stacking structure and at least one second chip stacking structure; and a plurality of second base plates. The first and second chip stacking structures are arranged side-by-side on the first semiconductor chip in a first direction, a plurality of second conductive bumps are formed on sides of the first and second chip stacking structure that is away from each other in the first direction, the first direction being parallel to a plane where the first base plate is located. A signal line in each second base plate is connected to the second conductive bumps. The second base plates are connected to the first base plate in a direction perpendicular to the plane where the first base plate is located.

Abstract: Embodiments provide a fabricating method, a semiconductor structure, and a semiconductor device. The method includes: providing a plurality of chips, each of the chips includes an element region and a scribe line region arranged in a first direction; stacking the chips to form a chip module, where a stacking direction of the chips is a second direction perpendicular to the first direction, the element regions of the chips are overlapped with each other, and the scribe line regions of the chips are overlapped with each other; planarizing a side surface of each of the scribe line regions distant from the element region after the chip module is formed, to remove at least part of the scribe line regions and expose the power supply wiring layer; and forming a pad on the side surface planarized, where the pad is connected to the power supply wiring layer.

Abstract: A semiconductor structure and a manufacturing method thereof are disclosed. The semiconductor structure includes a semiconductor substrate, a metal pad, a bump, a metal barrier layer, and a solder layer. The metal pad is arranged on the semiconductor substrate; the bump is arranged on the metal pad; the metal barrier layer is arranged on the side of the bump away from the metal pad; the metal barrier layer contains a storage cavity; the sidewall of the metal barrier layer is configured with an opening connecting to the storage cavity; the solder layer is arranged inside the storage cavity, and the top side of the solder layer protrudes from the upper side of storage cavity. During the flip-chip soldering process, solder is heated to overflow, the opening allows the solder flow out through the opening. The openings achieve good solder diversion in overflow, thus mitigating the problem of solder bridging between bumps.

Abstract: The disclosed semiconductor structure includes a semiconductor substrate, a metal pad, a bump, a first solder layer, a barrier layer, and a second solder layer. The metal pad is disposed on the semiconductor substrate; the bump is arranged on the metal pad; the barrier layer is configured on the side of the bump away from the metal pad. The barrier layer includes a first surface and a second surface. The first solder layer is arranged between the bump and the first surface of the barrier layer. The second solder layer is configured on the second surface of the barrier layer. Since the first solder layer and the second solder layer are formed by reflowed and melt solder at a high temperature and can be stretched, the height of the second solder can be adjusted automatically, which reduces the non-wetting problem caused by the package substrate deformation after reflow.

Abstract: Embodiments provide a semiconductor structure and a semiconductor memory, relating to the field of semiconductor technology. The semiconductor structure includes a substrate, active pillars spaced on the substrate, word lines spaced on the substrate along a second direction, and a dielectric layer covering the active pillars and the word lines. Each of the word lines extends along a first direction and is connected to the active pillars positioned in the first direction. In any adjacent two word lines, a groove is provided on a surface of at least one of the two adjacent word lines towards other one of the two adjacent word lines, and an air gap is provided in the dielectric layer positioned between adjacent word lines.

Abstract: A method for manufacturing a semiconductor device and a semiconductor device are provided. The method includes: providing a carrier; providing multiple wafers each including multiple chips; stacking the multiple wafers on the carrier sequentially in a vertical direction, and bonding the chips respectively disposed on two adjacent ones of the wafers in a one-to-one correspondence; performing a first cutting process on the multiple wafers to form multiple cutting slots located above the carrier and penetrating through the multiple wafers to divide the multiple wafers into multiple chip stacks each including multiple chips stacked in the vertical direction, and the carrier enabling the chip stacks to be in an un-separated state; forming a cladding layer covering at least one chip stack; and performing a second cutting process on the cladding layer along the cutting slots to form multiple chip stacks covered with the cladding layer.

Abstract: A wafer warpage adjustment structure is provided. The wafer warpage adjustment structure includes a wafer, a first dielectric layer, and a second dielectric layer. Each of the first and second dielectric layers includes at least a first area or a second area, and other areas other than at least the first area or the second area. The first area covers a portion of the wafer protruded in a direction perpendicular to a surface of the wafer and extending from the wafer to the dielectric layer, and the second area covers a portion of the wafer recessed in the direction. CTE of a material of the first area is greater than CTE of a material of the wafer, and CTE of a material of the second area is less than CTE of the material of the wafer. A method for manufacturing the same is also provided.

Abstract: A copper pillar bump structure on a copper pillar on a metal pad of a semiconductor device and a method of fabricating thereof are disclosed. The copper pillar bump structure includes: a metal barrier layer formed on the copper pillar. The metal barrier layer has a U-shaped cross section, a central portion of the metal barrier layer covers the top surface of the copper pillar, an opening of the U-shaped cross section faces away from the copper pillar. The copper pillar bump structure further includes a solder layer on the copper pillar and filling the U-shaped cross section. The copper pillar bump structure provides a metal barrier layer having a U-shaped cross section and fills a solder layer in the U-shaped cross section, the metal barrier layer wraps sides of the solder layer, which can improve the non-wetting problem caused by insufficient tin, or the solder bridging problem caused by excessive solder, during a flip die soldering process.

Abstract: A package structure includes the following: a logic die; and a plurality of core dies sequentially stacked on the logic die along a vertical direction, in which the plurality of core dies include a first core die and a second core die interconnected through a hybrid bonding member; the hybrid bonding member includes: a first contact pad located on a surface of the first core die; and a second contact pad located on a surface of the second core die; the first contact pad is in contact bonding with the second contact pad.

Abstract: A semiconductor package structure and a method for preparing the same are provided. The semiconductor package structure includes: a substrate; a first semiconductor chip located on the substrate, the first semiconductor chip having a first surface that is bare and the first surface having a silicon-containing surface; second semiconductor chip structures located on the first surface of the first semiconductor chip, the second semiconductor chip structures having second surfaces opposite to the first surface; a first package compound structure having a joint surface, the joint surface covering at least the first surface of the first semiconductor chip and the second surfaces of the second semiconductor chip structures. The joint surface has a silicon-containing surface.